ADN2531ACPZ-R2 Analog Devices Inc, ADN2531ACPZ-R2 Datasheet - Page 16

• Manufacturer Part Number: ADN2531ACPZ-R2
• Description: IC, LASER DIODE DRIVER, 11.3GBPS LFCSP16
• Manufacturer: Analog Devices Inc

Specifications of ADN2531ACPZ-R2

• Laser Driver Type: Laser Diode
• Supply Current: 36mA
• Bias Current: 100mA
• Modulation Current: 70mA
• Data Rate: 11.3Gbps
• Supply Voltage Range: 3V To 3.6V
• Driver Case Style: LFCSP
• No. Of Pins: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADN2531
LAYOUT GUIDELINES
Due to the high frequencies at which the ADN2531 o
care should be taken when designing the P
optimum performance. For example, use controlled impedance
transmission lines for high speed signal paths, and keep the
length of transmission lines as short as possible to reduce losses
and pattern-dependent jitter. In addition, the PCB layout must
be symmetrical, both on the DATAP and DATAN inputs and o
the IMODP and IMODN outputs, to ensure a balance between
the differential signals.
Furthermore, all VCC and GND pins must be connected to
solid copper planes by using low inductance connections. Wh
these connections are made through vias, multiple vias can be
connected in parallel to reduce the parasitic inductance. Each
GND pin must be locally decoupled to VCC with high quality
capacitors (see Figure 40). If proper decoupling cannot be
achieved using a single capacitor, u
parallel for each GND pin. A 20 μF tantalum capacitor must be
used as the general decoupling capacitor for the entire module.
For recommended PCB layouts, including those suitable for the
S
su
Application Note, A Design and Manufacturing Guide for the
Lead Frame Chip Scale Package (LFCSP) , on www.analog.com.
DESIGN EXAMPLE
Assuming that the impedance of the TOSA is 12 Ω, the forward
voltage of the laser at low current is V
I
•
•
•
Headroom Calculations
To ensure proper device operation, the voltages on the IBIAS,
IMODP, and IMODN pins must meet the compliance voltage
specifications in Table 1.
Considering the typical application circuit shown in Figure 40,
the voltage at the IBIAS pin can be written as
wher
V
V
R
V
For proper operation, the minimum voltage at the IBIAS pin
should be greater than 0.6 V, as specified by the minimum
IBIAS compliance specification in Table 1.
Assuming that the voltage drop across the 50 Ω transmission lines
is negligible and that V
MOD
FP+ and XFP modules, contact sales. For guidelines on the
TOSA
CC
F
LA
rface-mount assembly of the ADN2531, see the AN-772
is the forward voltage across the laser at low current.
is the dc voltage drop across L5, L6, L7, and L8.
is the supply voltage.
= 40 mA, and V
The headroom for the IBIAS, IMODP, and IMODN pins.
The typical voltage required at the BSET and MSET pins to
produce the desired bias and modulation currents.
The I
V
V
e:
is the resistance of the TOSA.
IBIAS
IBIAS
BIAS
= V
= 3.3 − 1.5 − (0.04 × 12) = 1.32 V
monitor accuracy over the I
CC
− V
F
CC
− ( I
LA
= 3.3 V, this design example calculates
BIAS
= 0 V, V
× R
TOSA
F
se multiple capacitors in
= 1.5 V, and I
) − V
F
= 1.5 V, I
LA
BIAS
CB layout to obtain
current range.
BIAS
BIAS
= 40 mA,
= 40 mA,
perates,
Rev. 0 | Page 16 of 20
en
n
Therefore, V
The maximum voltage at the IBIAS pin must be less than the
maximum IBIAS compliance specification as described by
For this example,
Therefore, V
requirement.
To calc
(IMODP and
to V du
I
operation of the ADN2531, t
output
in Figure 36.
Assum
and I
output pins is e
Therefore, V
requirement.
The maximum voltage at the modulation output pins is equal to
Therefore, V
requirement.
Headroom calculations must be repeated for the minimum and
maximum values of the required I
proper device operation over all operating conditions.
BSET and MSET Pin Voltage Calculations
To set the desired bias and modulation currents, the BSET and
MSET pins of the ADN2531 must be driven with the appropriate
dc voltage. The voltage range required at the BSET pin to generate
the required I
I
I
BSET voltage is given by
The BSET voltage range can be calculated using the required
I
I
The voltage required at the MSET pin to produce the desired
modulation current can be calculated using
where K is the MSET voltage to I
MOD
BIAS
BIAS
BIAS
BIAS
/V
gain specified in Table 1. Assuming that I
CC
range and the minimum and maximum BSET voltage to
gain values specified in Table 1.
V
V
V
V
× 5
V
V
MOD
BSET
COMPLIANCE_MAX
COMPLIANCE_MAX
CC
CC
BSET
MSET
ing the dc
ulate the h
pin should
0 Ω becau
− ( I
+ ( I
is 40
e to the ac-co led
= 100 mA/V (which is the typical I
=
=
IBIAS
IBIAS
MOD
MOD
100
CC
CC
I
BIAS
BIAS
I
IMO
mA,
MOD
qual
− 0.24 > V
+ 0.24 < V
K
= 1.32 V > 0.6 V, which satisfies the requirement
= 1.32 V < 2.374 V, which s
range can be calculated using the BSET voltage to
× 12)/2 = V
× 12)/2 = V
mA/V
vo
(mA)
eadroom t the modulation c
se R
be with the normal operation
DN), t
the mi
ltage dro
= V
= V − 0.75 − 4.4 × 0.04 = 2.374 V
to
TOSA
up
=
CC
CC
100
he
nim
CC
CC
40
− 0.75 − 4.4 × I
in
is
a
CC
− 1.1 V, which satisfies the
CC
+ 1.1 V, which satisfies the
voltage has a dc component equal
p across L1, L2, L3, and L4 is 0 V
less than 100 Ω. For p
he voltage at each modulation
configuration and a swing equal to
=
um voltage at the m
− 0.24 V
+ 0.24 V
0
4 .
MOD
BIAS
V
ratio.
and I
BIAS
atisfies the
BIAS
MOD
BIAS
(A)
/V
= 40 mA and that
urrent pins
ranges to ensure
BSET
odulation
roper
region shown
ratio), the