CS4341-KS Cirrus Logic Inc, CS4341-KS Datasheet - Page 3

• Manufacturer Part Number: CS4341-KS
• Description: IC, DAC, 24BIT, 96KSPS, SOIC-16
• Manufacturer: Cirrus Logic Inc

Specifications of CS4341-KS

• Resolution (bits): 24bit
• Sampling Rate: 96kSPS
• Input Channel Type: Serial
• Supply Current: 15mA
• Digital Ic Case Style: SOIC
• No. Of Pins: 16
• Data Interface: Serial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LIST OF FIGURES
DS298PP2
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10. Base-Rate Transition Band .......................................................................................... 28
Figure 11. Base-Rate Transition Band (Detail) ............................................................................. 28
Figure 12. Base-Rate Passband Ripple ........................................................................................ 28
Figure 13. High-Rate Stopband Rejection .................................................................................... 28
Figure 14. High-Rate Transition Band ........................................................................................... 28
Figure 15. High-Rate Transition Band (Detail) .............................................................................. 29
Figure 16. High-Rate Passband Ripple ......................................................................................... 29
Figure 17. Output Test Load ......................................................................................................... 29
6. APPLICATIONS ..................................................................................................................... 25
7. CONTROL PORT INTERFACE .............................................................................................. 26
8. PARAMETER DEFINITIONS .................................................................................................. 33
9. REFERENCES ........................................................................................................................ 33
10. PACKAGE DIMENSIONS .................................................................................................... 34
Analog Output - AOUTA and AOUTB..................................................................................... 22
Reference Ground - REF_GND.............................................................................................. 22
Positive Voltage Reference - FILT+........................................................................................ 22
Quiescent Voltage - VQ .......................................................................................................... 22
Master Clock - MCLK ............................................................................................................. 23
Left/Right Clock - LRCK ......................................................................................................... 23
Serial Audio Data - SDATA .................................................................................................... 23
Serial Clock - SCLK ................................................................................................................ 24
Reset - RST............................................................................................................................ 24
Serial Control Interface Clock - SCL/CCLK ........................................................................... 24
Serial Control Data I/O - SDA/CDIN ....................................................................................... 24
Address Bit / Chip Select - AD0/CS........................................................................................ 24
Mute Control - MUTEC ........................................................................................................... 24
6.1 Grounding and Power Supply Decoupling ....................................................................... 25
6.2 Oversampling Modes ....................................................................................................... 25
6.3 Recommended Power-up Sequence ............................................................................... 25
6.4 Use of the Power ON/OFF Quiescent Voltage Ramp ..................................................... 25
7.1 SPI Mode ......................................................................................................................... 26
7.2 I
7.2 Memory Address Pointer (MAP) ....................................................................................... 27
Total Harmonic Distortion + Noise (THD+N) .......................................................................... 33
Dynamic Range ...................................................................................................................... 33
Interchannel Isolation ............................................................................................................. 33
Interchannel Gain Mismatch ................................................................................................... 33
Gain Error ............................................................................................................................... 33
Gain Drift ................................................................................................................................ 33
2
C Compatible Mode ...................................................................................................... 26
External Serial Mode Input Timing ................................................................................. 9
Internal Serial Mode Input Timing .................................................................................. 9
Internal Serial Clock Generation .................................................................................... 9
I
SPI Control Port Timing ............................................................................................... 11
Typical Connection Diagram ........................................................................................ 12
SPI Mode Control Port Formating ................................................................................ 27
I
Base-Rate Stopband Rejection .................................................................................... 28
2
2
C Control Port Timing ................................................................................................ 10
C Mode Control Port Formating ................................................................................ 27
CS4341
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