CS5360-KS Cirrus Logic Inc, CS5360-KS Datasheet
CS5360-KS
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CS5360-KS Summary of contents
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... This ADC uses a differential architecture which provides excellent noise rejection. The CS5360 has a filter passband to 21.7 kHz. The filter has linear phase, 0.0025 dB passband ripple, and >85 dB stopband rejection. An on-chip high pass filter is also included to remove DC offsets. ORDERING INFORMATION CS5360-KS CS5360-BS VD+ RST MCLK OVFL FRAME ...
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... Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com. 2 CS5360 DS280PP2 ...
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... Figure 11. Full Scale Input Levels................................................................................................. 10 Figure 12. CS5360 Digital Filter Passband Ripple........................................................................ 14 Figure 13. CS5360 Digital Filter Transition Band.......................................................................... 14 Figure 14. CS5360 Digital Filter Stopband Rejection.................................................................... 14 Figure 15. CS5360 Digital Filter Transition Band.......................................................................... 14 LIST OF TABLES Table 1. Common Clock Frequencies............................................................................................. 9 Table 2. Digital Input Formats ......................................................................................................... 9 Table 3. Peak Signal Level Bits - High Resolution Mode.............................................................. 12 Table 4 ...
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... Max Min Typ Max - 105 - 92 102 -95 -90 - -95 -82 -77 - -82 -42 - 105 - - 0.05 - ± 200 ±100 2.0 2.1 1 0.5 375 - 325 2 2 CS5360 Units ° -85 dB - Degree - ± ppm/°C - LSB - LSB 2.1 Vrms - 375 DS280PP2 ...
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... VA ±5%) A Symbol (VD (AGND = 0 V, all voltages with respect to ground.) Symbol VA+ (Note (Note 6) V INA (Note 6) V IND stg CS5360 Min Typ Max Unit 0.02 - 21.7 kHz - - ±0.0025 dB 26.3 - 6118 kHz 32/ µ 2.6 - Degree ...
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... MCLK / LRCK = 512 pu pulse (Note 7) t mslr (Note 7) t sdo (Note 7) t sfo t ovfl t ovfl t sclkw (Note 10) t sclkl (Note 11) t sclkh (Note 7) t dss t lrdss (Note 14) t slr1 (Note 14) t slr2 t sfo CS5360 Min Typ Max Unit 8 kHz 78 - 1953 1302 39 - 976 ...
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... SCLK input (SLAVE mode) t sclkw LRCK input (SLAVE mode) t dss MSB-1 MSB-2 Figure 4. SCLK to LRCK & SDATA - SLAVE Mode t mslr OVFL Format slr1 slr2 sclkl sclkh t dss SDATA MSB t ovfl OVFL Format 2 CS5360 t sdo MSB t ovfl t sclkw MSB-1 7 ...
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... VA+ OVFL CS5360 17 AINL+ 16 AINL- HP DEFEAT DIF0 15 DIF1 CMOUT SDATA 13 AINR+ LRCK 14 AINR- SCLK MCLK RST FRAME DGND AGND 5 4 Figure 6. Typical Connection Diagram CS5360 +5V Analog + 0 Peak Signal Level Monitor Mode 20 Settings 19 100 9 Audio Data Processing 100 12 100 8 Timing, Logic & 100 ...
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... Table 1. Common Clock Frequencies DS280PP2 3. SERIAL DATA INTERFACE The CS5360 supports three serial data formats, in- 2 cluding I S, selected via the digital interface format pins DIF0 and DIF1. The digital interface format de- termines the relationship between the serial data, left/right clock and serial clock ...
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... Data Valid on Rising Edge of SCLK MCLK equal to 256x, 384x, or 512x Fs Figure 8. Serial Data Format 0 LEFT SLAVE Figure 9. Serial Data Format 24-Bit Left Justified Data Data Valid on Rising Edge of SCLK MCLK equal to 256x, 384x, or 512x Fs Figure 10. Serial Data Format 2 CS5360 RIGHT SLAVE RIGHT RIGHT ...
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... Clock. Internal dividers will divide MCLK generate a SCLK which is 64x Fs and by 256 to generate a LRCK which is equal to Fs. Master mode is only supported with a 256x master clock. The CS5360 is placed in the Master mode with pull-down resistor on the OVFL pin. 3.5 Slave Mode LRCK and SCLK become inputs in SLAVE mode. ...
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... CS5360, 2) running the CS5360 with the HP DEFEAT pin low (high pass filter enabled) until the filter set- tles (approximately 1 second), and 3) taking the HP DEFEAT pin high, disabling the high pass filter and freezing the stored dc off- set ...
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... This procedure takes 4,160 cycles of LRCK. Un- like the system calibration procedure described in the High Pass Filter section calibration per- formed during start-up will only eliminate offsets internal to the CS5360, and should result in output codes which accurately reflect the differential dc signal at the pins. CS5360 ...
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... All mode pins which re- quire VD+ should be connected to pin 6 of the CS5360. All mode pins which require DGND should be connected to pin 5 of the CS5360. AGND and DGND, Pins 4 and 5, should be con- nected together at the CS5360. DGND for the CS5360 should not be confused with the ground for 14 the digital section of the system ...
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... Figure 12. CS5360 Digital Filter Passband Ripple Figure 14. CS5360 Digital Filter Stopband Rejection DS280PP2 Figure 13. CS5360 Digital Filter Transition Band Figure 15. CS5360 Digital Filter Transition Band CS5360 15 ...
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... The left channel information is output on OVFL during the left channel portion of LRCK. The right channel information is available on OVFL during the right channel portion of LRCK. The registers are updated with a high to low transition on the PEAK UPDATE pin will set the CS5360 in Master Mode. Positive Analog Power - VA+ Pin 3, Input Function: Positive analog supply ...
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... LRCK, SCLK and SDATA is controlled by DIF0 and DIF1. Although the outputs for each channel are transmitted at different times, Left/Right pairs represent simultaneously sampled analog inputs. In Master Mode, LRCK is an output clock whose frequency is equal to the output sample rate, Fs. In Slave Mode, LRCK is an input clock whose frequency must be equal to Fs. DS280PP2 CS5360 17 ...
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... Pin 15, Output Function: This output, nominally 2.2 V, can be used to bias the analog input circuitry to the common mode voltage of the CS5360. CMOUT is not buffered and the maximum current is 10 µA. Differential Left Channel Analog Input - AINL+, AINL- Pin 16 and Pin 17, Input Function: Analog input connections of the left channel differential inputs ...
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... The deviation from the nominal full-scale analog input for a full-scale digital output. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV. DS280PP2 CS5360 19 ...
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... MIN MAX -- 0.084 0.002 0.010 0.064 0.074 0.009 0.015 0.272 0.295 0.291 0.323 0.197 0.220 0.024 0.027 0.025 0.040 0° 8° CS5360 1 E1 END VIEW L MILLIMETERS NOTE MIN MAX -- 2.13 0.05 0.25 1.62 1.88 0.22 0.38 2,3 6.90 7.50 1 7.40 8.20 5 ...
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Notes • ...
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