78Q8430-100CGT/F TERIDIAN, 78Q8430-100CGT/F Datasheet - Page 8

• Manufacturer Part Number: 78Q8430-100CGT/F
• Description: IC, ETHERNET TXRX, IEEE 802.3, LQFP-100
• Manufacturer: TERIDIAN

Specifications of 78Q8430-100CGT/F

• No. Of Ports: 2
• Ethernet Type: IEEE 802.3x, IEEE 802.3u, IEEE 802.3-2000
• Ic Interface Type: Host Bus, JTAG
• Supply Voltage Range: 0V To 3.3V
• Operating Temperature Range: 0°C To +70°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SIGNAL
RX_DV
RXD[3:0]
RX_ER
MDC
MDIO
SIGNAL
MII (MEDIA INDEPENDENT INTERFACE) (CONTINUED)
CONTROL AND STATUS
Page: 8 of 39
RSTN
INTR
PIN
11
[5:8]
13
2
1
PIN
23
32
TYPE DESCRIPTION
COZ
COZ
COZ
CIS
CIO
TYPE DESCRIPTION
CIS
COZ
RECEIVE DATA VALID: RX_DV is asserted high to indicate that valid data is
present on the RXD[3:0] pins. In 100BASE-TX mode, it transitions high with the first
nibble of the preamble and is pulled low when the last data nibble has been
received. In 10BASE-T mode it transitions high when the start-of-frame delimiter
(SFD) is detected. This pin is tri-stated in isolate mode.
RECEIVE DATA: Received data is provided to the MAC via RXD[3:0]. These pins
are tri-stated in isolate mode.
RECEIVE ERROR: RX_ER is asserted high when an error is detected during frame
reception. In PCS bypass mode, this pin becomes the MSB of the receive 5-bit code
group. This pin is tri-stated in isolate mode.
MANAGEMENT DATA CLOCK: MDC is the clock used for transferring data via the
MDIO pin.
MANAGEMENT DATA INPUT/OUTPUT: MDIO is a bi-directional port used to
access management registers within the 78Q2123/78Q2133. This pin requires an
external pull-up resistor as specified in IEEE-802.3.
ACTIVE LOW RESET: When pulled low the pin resets the chip. The reset pulse
INTERRUPT PIN: This pin is used to signal an interrupt to the media access
must be long enough to guarantee stabilization of the supply voltage and startup of
the oscillator. Refer to the Electrical Specifications for the reset pulse requirements.
There are 2 other ways to reset the chip:
controller. The pin is held in the high impedance state when an interrupt is not
indicated. The pin will be forced high or low to signal an interrupt depending upon
the value of the INPOL bit (MR16.14). The events which trigger an interrupt can be
programmed via the Interrupt Control Register located at address MR17.
ii. Through the MII register bit (MR 0.15)
i. Through the internal power-on-reset (activated when the chip is being powered
up)
©
2006 Teridian Semiconductor Corporation
10/100BASE-TX Transceiver
Rev 1.1