SKY12340-364LF Skyworks Solutions Inc, SKY12340-364LF Datasheet - Page 3

• Manufacturer Part Number: SKY12340-364LF
• Description: ATTENUATOR DGTL GAAS 5BIT QFN-32
• Manufacturer: Skyworks Solutions Inc

Specifications of SKY12340-364LF

• Attenuation Value: 0.5dB ~ 15.5dB
• Tolerance: ±0.35dB
• Frequency Range: 300kHz ~ 2GHz
• Impedance: 50 Ohm
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 863-1295-2

Functional Description
The SKY12340-364LF is a five bit digital attenuator comprised of
a GaAs attenuator and a silicon CMOS driver. The attenuation
setting is controlled by a serial-to-parallel interface. Attenuation is
set by a stream of data that is clocked into the shift registers of
the silicon chip by the clock signal.
To set the attenuation state, a latch signal is sent to the
appropriate pin to send the correct bias voltages to the GaAs
attenuator. The silicon chip generates a negative voltage using a
negative voltage generator that requires two external
components: a charge pump capacitor connected between pins
30 (C2) and 31 (C1) and a voltage hold capacitor connected from
pin 28 (VSS) to ground.
More than one attenuator can be cascaded together and the data
may be passed through one device to the other using the
DATA_OUT signal (pin 1). To reset the attenuator to the insertion
loss state, a logic low signal may be sent to the reset pin. DC bias
voltage to the silicon CMOS chip is applied to pin 32 (VDD).
Power-Up/Power-Down Timing
Serial data (SDA) is shifted into the register on the rising edge of
the clock (SCK), least significant bit (LSB) first. The attenuator
Table 2. Power-Up/Power-Down Timing Parameters
LE setup time
SDA setup time
SDA hold time
LE hold time
Clock frequency
Clock period
Parameter
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
201111B • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 5, 2010
SCK
SDA
LE
T1
T1
T2
T3
T4
f
T5
CLK
T2
Symbol
Figure 3. Power-Up/Power-Down Timing
T3
Data Feedthrough
Minimum
7.5
7.5
5
5
T5
changes states on the rising edge of the latch-enable (LE) signal,
according to the most recent five bits of shifted data accepted
since the previous falling edge of the LE signal. Refer to the
timing diagram in Figure 3 and timing parameter specifications in
Table 2.
Power-up sequence is as follows:
0. Connect ground
1. Apply VDD
2. Set all inputs (SCK, SDA, LE)
The power-down sequence is the reverse of above.
Electrical and Mechanical Specifications
The absolute maximum ratings of the SKY12340-364LF are
provided in Table 3. Electrical specifications are provided in
Tables 4 and 5.
Typical performance characteristics of the SKY12340-364LF are
illustrated in Figures 4 through 10.
The state of the SKY12340-364LF is determined by the logic
provided in Table 6.
DATA SHEET • SKY12340-364LF FIVE-BIT DIGITAL ATTENUATOR
Typical
1/f
15
15
10
10
16
CLK
Maximum
T4
100
S1594
Units
MHz
ns
ns
ns
ns
3