AGLN250V2-VQG100 Actel, AGLN250V2-VQG100 Datasheet - Page 60

FPGA - Field Programmable Gate Array 250K System Gates IGLOO nano

AGLN250V2-VQG100

Manufacturer Part Number
AGLN250V2-VQG100
Description
FPGA - Field Programmable Gate Array 250K System Gates IGLOO nano
Manufacturer
Actel
Datasheet

Specifications of AGLN250V2-VQG100

Processor Series
AGLN250
Core
IP Core
Number Of Macrocells
2048
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
68
Data Ram Size
36 Kbit
Supply Voltage (max)
1.5 V
Supply Current
34 uA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
Mounting Style
SMD/SMT
Supply Voltage (min)
1.2 V
Number Of Gates
250 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AGLN250V2-VQG100
Manufacturer:
Actel
Quantity:
135
Part Number:
AGLN250V2-VQG100
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
AGLN250V2-VQG100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
IGLOO nano DC and Switching Characteristics
Table 2-73 • Input Data Register Propagation Delays
2- 46
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
ICLKQ
ISUD
IHD
ICLR2Q
IPRE2Q
IREMCLR
IRECCLR
IREMPRE
IRECPRE
IWCLR
IWPRE
ICKMPWH
ICKMPWL
For specific junction temperature and voltage supply levels, refer to
Commercial-Case Conditions: T
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width HIGH for the Input Data Register
Clock Minimum Pulse Width LOW for the Input Data Register
1.2 V DC Core Voltage
J
= 70°C, Worst-Case VCC = 1.14 V
Description
R ev i sio n 1 1
Table 2-7 on page 2-7
for derating values.
0.68
0.97
0.00
1.19
1.19
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
Std.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Related parts for AGLN250V2-VQG100