ISL21400USB-EVALZ Intersil, ISL21400USB-EVALZ Datasheet - Page 12

• Manufacturer Part Number: ISL21400USB-EVALZ
• Description: EVAL BOARD FOR ISL21400
• Manufacturer: Intersil

Specifications of ISL21400USB-EVALZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

All communication over the I
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (see
Figure 10). On power-up of the ISL21400 the SDA pin is in
the input mode.
All I
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL21400 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (see
Figure 10). A START condition is ignored during the
power-up sequence and during non-volatile write cycles for
the device.
All I
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (see Figure 10) A STOP condition at the end of
a read operation, or at the end of a write operation places
the device in its standby mode. A STOP condition at the end
of a write operation to a non-volatile byte initiates an internal
non-volatile write cycle. The device enters its standby state
when the internal, non-volatile write cycle is completed.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (see Figure 11).
The ISL21400 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL21400 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
A valid Identification Byte contains 0101 A2 A1 A0 as the
seven MSBs. The A2 A1 A0 bits must correspond to the
logic levels at those pins of the ISL21400 device. The LSB in
the Read/Write bit. Its value is “1” for a Read operation, and
“0” for a Write operation (see Table 4).
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL21400 responds with an ACK. The master will then send
a STOP and at this time the device begins its internal
(MSB)
2
2
0
C interface operations must begin with a START
C interface operations must be terminated by a STOP
TABLE 4. IDENTIFICATION BYTE FORMAT
1
0
1
2
12
C interface is conducted by
A2
A1
A0
(LSB)
R/W
ISL21400
non-volatile write cycle. During this time, the device ignores
transitions at the SDA and SCL pins, and the SDA output is
at a high impedance state. When the internal non-volatile
write cycle is completed, the ISL21400 enters its standby
state (see Figure 12).
STOP conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte and
its associated ACK signal. If a STOP byte is issued in the
middle of a data byte, or before 1 full data byte + ACK is
sent, then the ISL21400 resets itself without performing the
write. The contents of the array are not affected.
Data Protection
A valid Identification Byte, Address Byte, and total number of
SCL pulses act as a protection for the registers. A STOP
condition also acts as a protection for non-volatile memory.
During a Write sequence, the Data Byte is loaded into an
internal shift register as it is received. The presence of the
STOP condition after the rest of the bits are received then
triggers the non-volatile write.
Read Operation
A Current Address Read operation is shown in Figure 13. It
consists of a minimum 2 bytes: a START followed by the ID
byte from the master with the R/W bit set to 1, then an ACK
followed by the data byte or bytes sent by the slave. The
master terminates the Read operation by not responding
with an ACK and then issuing a STOP condition. This
operation is useful if the master knows the current address
and desires to read one or more data bytes.
A Random Address Read operation consists of a three byte
“dummy write” instruction followed by a Current Address
Read operation (see Figure 14). The master initiates the
operation issuing the following sequence: a START, the
identification byte with the R/W bit set to "0", an Address
Byte, a second START, and a second Identification byte with
the R/W bit set to "1". After each of the three bytes, the
ISL21400 responds with an ACK. The ISL21400 then
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eighth bit of each
byte. The master terminates the Read operation (issuing a
STOP condition) following the last bit of the last Data Byte
(see Figure 13).
The Data Bytes are from the registers indicated by an
internal pointer. This pointer initial’s value is determined by
the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
Address 04h is the last valid data byte, higher addresses are
not available. Data from addresses higher than memory
location 04h will be invalid.
March 31, 2011
FN8091.3