RT8251GSP Richtek USA Inc, RT8251GSP Datasheet - Page 11

• Manufacturer Part Number: RT8251GSP
• Description: IC DCDC CTRLR STP-DN 8SOP
• Manufacturer: Richtek USA Inc
• Type: Step-Down (Buck)r

Specifications of RT8251GSP

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.8 V ~ 15 V
• Current - Output: 5A
• Frequency - Switching: 570kHz
• Voltage - Input: 4.75 V ~ 24 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width) Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

recovery time, V
ringing that would indicate a stability problem.
EMI Consideration
Since parasitic inductance and capacitance effects in PCB
circuitry would cause a spike voltage on the SW pin when
high-side MOSFET is turned-on/off, this spike voltage on
SW may impact on EMI performance in the system. In
order to enhance EMI performance, there are two methods
to suppress the spike voltage. One is to place an R-C
snubber between SW and GND and make them as close
DS8251-01 March 2011
Thermal Considerations
For continuous operation, do not exceed the maximum
operation junction temperature 125 C. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
P
Where T
temperature , T
the junction to ambient thermal resistance.
For recommended operating conditions specification of
RT8251, the maximum junction temperature is 125 C. The
junction to ambient thermal resistance
dependent. For PSOP-8 and WQFN packages, the thermal
resistance
JEDEC 51-7 four-layers thermal test board. The maximum
power dissipation at T
following formula :
D(MAX)
= (T
J(MAX)
J(MAX)
JA
are 75 C/W and 68 C/W on the standard
A
OUT
is the maximum operation junction
is the ambient temperature and the
4.75V to 24V
Chip Enable
T
A
can be monitored for overshoot or
* : Optional
) /
V
A
IN
Figure 5. Reference Circuit with Snubber and Enable Timing Control
JA
= 25 C can be calculated by
C
10nF
R
SS
C
EN
EN
*
*
Exposed Pad(9)
10µF x 2
C
IN
JA
4,
2
7
8
VIN
EN
SS
GND
is layout
RT8251
JA
is
COMP
BOOT
SW
FB
1
3
5
6
as possible to the SW pin (see Figure 5). Another method
is to add a resistor in series with the bootstrap capacitor,
C
to the high-side MOSFET. It is strongly recommended to
reserve the R-C snubber during PCB layout for EMI
improvement. Moreover, reducing the SW trace area and
keeping the main power in a small loop will be helpful on
EMI performance. For detailed PCB layout guide, please
refer to the section of Layout Consideration.
P
PSOP-8
P
WQFN
(min.copper area PCB layout)
P
PSOP-8 (70mm
The thermal resistance
determined by the package architecture design and the
PCB layout design. However, the package architecture
design had been designed. If possible, it's useful to
increase thermal performance by the PCB layout copper
design. The thermal resistance
adding copper area under the exposed pad of SOP-8
(Exposed Pad) package.
As shown in Figure 6, the amount of copper area to which
the SOP-8 (Exposed Pad) is mounted affects thermal
performance. W hen mount ed to the standard
D(MAX)
D(MAX)
D(MAX)
BOOT
R
BOOT
R
C
S
S
*
. But this method will decrease the driving capability
*
*
2.2nF
C
= (125 C
C
= (125 C
= (125 C
C
100nF
C
NC
D
B330A
BOOT
P
22k
R
C
4.7µH
2
copper area PCB layout)
L
25 C) / (75 C/W) = 1.333W for
25 C) / (68 C/W) = 1.471W for
25 C) / (49 C/W) = 2.04W for
10k
R1
30.9k
R2
JA
of SOP-8 (Exposed Pad) is
C
22µF x 2
OUT
JA
V
3.3V/5A
OUT
can be decreased by
RT8251
www.richtek.com
11