RT9259AGS Richtek USA Inc, RT9259AGS Datasheet - Page 12

• Manufacturer Part Number: RT9259AGS
• Description: IC CTRLR PWM SYNC BUCK 14SOP
• Manufacturer: Richtek USA Inc

Specifications of RT9259AGS

• Topology: Step-Down (Buck) Synchronous (1), Linear (LDO) (1)
• Function: Any Function
• Number Of Outputs: 2
• Frequency - Switching: 300kHz
• Voltage/current - Output 1: Controller
• Voltage/current - Output 2: Controller
• W/led Driver: No
• W/supervisor: No
• W/sequencer: No
• Voltage - Supply: 10.8 V ~ 13.2 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RT9259A
The ESR zero is contributed by the ESR associated with
the output capacitance. Note that this requires that the
output capacitor should have enough ESR to satisfy stability
requirements. The ESR zero of the output capacitor
expressed as follows :
2) Compensation Frequency Equations
The compensation network consists of the error amplifier
and the impedance networks Z
Figure 9.
Figure 10 shows the DC-DC converter's gain vs. frequency.
The compensation gain uses external impedance networks
Z
crossover frequency is desirable for fast transient response,
but often jeopardize the system stability. In order to cancel
one of the LC filter poles, place the zero before the LC
filter resonant frequency. In the experience, place the zero
at 75% LC filter resonant frequency. Crossover frequency
should be higher than the ESR zero but less than 1/5 of
the switching frequency. The second pole is placed at half
the switching frequency.
www.richtek.com
12
f
f
f
ESR
P1
C
Z1
and Z
=
=
=
2
2
π
π
2
F
π
COMP
x
x
to provide a stable, high bandwidth loop. High
×
R2
R2
1
C
Figure 9. Compensation Loop
R2
OUT
x
1
x
1
EA
C1
C1
C2
C1
Z
F
-
+
×
V
C2
+
x
REF
ESR
C2
C2
FB
R
F
Z
R1
C
C
and Z
F
as shown in
V
OUT
Thermal Considerations
For continuous operation, do not exceed absolute
maximum operation junction temperature 125°C. The
maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient. The maximum power dissipation can
be calculated by following formula :
P
Where T
temperature 125°C, T
θ
The junction to ambient thermal resistance θ
dependent. For SOP-14 packages, the thermal resistance
θ
thermal test board.
The maximum power dissipation at T
calculated by following formula :
P
SOP-14 packages
The maximum power dissipation depends on operating
ambient temperature for fixed T
θ
curves allows the designer to see the effect of rising
ambient temperature on the maximum power allowed.
JA
JA
JA
D(MAX)
D(MAX)
. For RT9259A packages, the Figure 11 of derating
is the junction to ambient thermal resistance.
is 100°C/W on the standard JEDEC 51-7 four-layers
-20
-40
-60
80
60
40
20
0
- 4 0
- 6 0
= ( T
8 0
4 0
0
1 0 H z
10
= ( 125°C − 25°C) / 100°C/W = 1.000 W for
Modulator
v d b ( v o ) v d b ( c o m p 2 ) v d b ( l o )
J(MAX)
Gain
J(MAX)
100
1 0 0 H z
is the maximum operation junction
Loop Gain
Figure 10. Bode Plot
− T
A
A
is the ambient temperature and the
) / θ
1 . 0 K H z
1k
Frequency (Hz)
JA
F r e q u e n c y
J(MAX)
DS9259A-02 March 2007
1 0 K H z
10k
and thermal resistance
Compensation
A
100k
1 0 0 K H z
= 25°C can be
Gain
JA
1 . 0 M H z
1M
is layout