PC28F640J3D75A NUMONYX, PC28F640J3D75A Datasheet - Page 31

• Manufacturer Part Number: PC28F640J3D75A
• Description: IC FLASH 64MBIT 75NS 64EZBGA
• Manufacturer: NUMONYX

Specifications of PC28F640J3D75A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 64M (8Mx8, 4Mx16)
• Speed: 75ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 875776; 875776; PC28F640J3D75 875776

Numonyx™ Embedded Flash Memory (J3 v. D)
8.0
Table 14: Bus Operations
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Table 15: Chip Enable Truth Table
November 2007
308551-05
Async., Status, Query and Identifier
Reads
Output Disable
Standby
Reset/Power-down
Command Writes
Array Writes
Note:
See
OE# and WE# should never be asserted simultaneously. If done so, OE# overrides WE#.
DQ refers to DQ[7:0} when BYTE# is low and DQ[15:0] if BYTE# is high.
Refer to DC characteristics. When V
X should be V
In default mode, STS is V
algorithm. It is V
suspend mode (with programming inactive), program suspend mode, or reset power-down mode.
See
operation
Array writes are either program or erase operations. /
For single-chip applications, CE2 and CE1 can be connected to
Table 15
Table 18, “Command Bus Operations” on page 35
(8)
CE2
V
V
V
V
V
V
V
V
IH
IH
IH
IH
IL
IL
IL
IL
Mode
Bus Interface
This section provides an overview of Bus operations. Basically, there are three operations you can
do with flash memory: Read, Program (Write), and Erase.The on-chip Write State Machine
(WSM) manages all erase and program algorithms. The system CPU provides control of all in-system read,
write, and erase operations through the system bus. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
states of each control signal for different modes of operations.
The next few sections detail each of the basic flash operations and some of the
advanced features available on flash memory.
IL
for valid CE
or V
OH
(pulled up by an external pull up resistance ~= 10k) when the WSM is not busy, in block erase
IH
for the control pins and V
OL
x
when the WSM is executing internal block erase, program, or a lock-bit configuration
Configurations.
RP#
V
V
V
V
V
V
PEN
IH
IH
IH
IH
IH
IL
CE1
V
V
V
V
V
V
V
V
IH
IH
IH
IH
IL
IL
IL
IL
≤
Enabled
Enabled
Enabled
Enabled
Disable
CE
V
PENLK
d
X
x
PENLK
(1)
, memory contents can be read but not altered.
or V
OE#
V
V
V
V
X
X
IH
IH
IH
PENH
IL
(2)
for V
GND
WE#
V
V
V
V
PEN
.
X
X
IH
IH
IL
IL
for valid DIN (user commands) during a Write
(2)
. For outputs, X should be V
CE0
V
V
V
V
V
V
V
V
Table 14
IH
IH
IH
IH
IL
IL
IL
IL
V
V
PENH
PEN
X
X
X
X
X
summarizes the necessary
DQ
High Z
High Z
High Z
D
D
3)
OUT
15:0
X
IN
(
OL
(Default
Mode)
High Z
High Z
High Z
High Z
High Z
or V
DEVICE
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
STS
V
IL
OH
.
Datasheet
Notes
4,6
6,7
8,5
31