AGL400V5-FGG484 Actel, AGL400V5-FGG484 Datasheet - Page 24

• Manufacturer Part Number: AGL400V5-FGG484
• Description: FPGA - Field Programmable Gate Array 400K System Gates
• Manufacturer: Actel

Specifications of AGL400V5-FGG484

• Processor Series: AGL400
• Core: IP Core
• Number Of Logic Blocks: 12
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 194
• Data Ram Size: 54 Kbit
• Supply Voltage (max): 1.5 V
• Supply Current: 27 uA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 400 K
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IGLOO DC and Switching Characteristics
Table 2-12 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
2- 10
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
Notes:
1. P
2. P
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
4. Applicable for IGLOO V2 devices only
Single-Ended
Notes:
1. P
2. P
3. Applicable for IGLOO V2 devices only.
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3.3V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
1.2 V LVCMOS
1.2 V LVCMOS Wide Range
3.3 V PCI
3.3 V PCI-X
Differential
LVDS
LVPECL
3.3 V LVTTL / 3.3 V LVCMOS
3.3V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
1.2 V LVCMOS
1.2 V LVCMOS Wide Range
3.3 V PCI
3.3 V PCI-X
DC6
AC9
DC6
AC9
is the total dynamic power measured on VCCI.
is the total dynamic power measured on VCCI.
is the static power (where applicable) measured on VCCI.
is the static power (where applicable) measured on VCCI.
Power per I/O Pin
Applicable to Advanced I/O Banks
Applicable to Standard Plus I/O Banks
4
4
3
3
4
4
VCCI (V)
VCCI (V)
1.2
1.2
1.2
1.2
3.3
3.3
2.5
1.8
1.5
3.3
3.3
2.5
3.3
3.3
3.3
2.5
1.8
1.5
3.3
3.3
R ev i sio n 1 8
Static Power
PDC6 (mW)
Static Power
PDC6 (mW)
2.26
5.72
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
1
PAC9 (µW/MHz)
PAC9 (µW/MHz)
Dynamic Power
Dynamic Power
16.27
16.27
17.67
17.67
23.39
59.05
16.41
16.41
17.78
17.78
4.65
1.61
0.96
0.58
0.58
4.75
1.66
1.00
0.61
0.61
2
2