PCA9554ABS3,118 NXP Semiconductors, PCA9554ABS3,118 Datasheet - Page 10

• Manufacturer Part Number: PCA9554ABS3,118
• Description: I2C Interface IC 8-BIT I2C FM TP GPIO
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of PCA9554ABS3,118

• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: HVQFN EP
• Mounting Type: Surface Mount
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Interface: I²C, SMBus
• Number Of I /o: 8
• Frequency - Clock: 400kHz
• Interrupt Output: Yes
• Includes: POR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935283049118 PCA9554ABS3-T

NXP Semiconductors
PCA9554_9554A_7
Product data sheet
Fig 12. Write to Output Port register
Fig 13. Write to Configuration register or Polarity Inversion register
write to port
from port
register
data out
data to
SDA
SCL
SDA
SCL
S
START condition
S
START condition
6.5 Device address
6.6 Bus transactions
1
1
0
0
2
1
2
1
Data is transmitted to the PCA9554/PCA9554A registers using the Write mode as shown
in
the Read mode as shown in
auto-increment function, so once a command byte has been sent, the register which was
addressed will continue to be accessed by reads until a new command byte has been
sent.
slave address
slave address
Fig 10. PCA9554 device address
3
0
3
Figure 12
0
4
4
0 A2 A1 A0 0
0 A2 A1 A0 0
5
5
0
6
acknowledge
6
acknowledge
from slave
1
and
from slave
7
fixed
7
R/W
R/W
slave address
8
0
8
Figure
9
A
9
A
0
Rev. 07 — 13 November 2006
0
0
A2
13. Data is read from the PCA9554/PCA9554A registers using
selectable
hardware
0
0
A1
command byte
0
command byte
Figure 14
0
002aac494
0
A0 R/W
0
0
0
acknowledge
acknowledge
0
0
from slave
and
from slave
8-bit I
1 1/0
0
Figure
1
A
2
A
PCA9554/PCA9554A
Fig 11. PCA9554A device address
C-bus and SMBus I/O port with interrupt
15. These devices do not implement an
0
data to register
data to port
DATA 1
DATA
1
fixed
slave address
1
acknowledge
acknowledge
from slave
from slave
1
t
v(Q)
programmable
A2
© NXP B.V. 2006. All rights reserved.
A
A
A1
002aac473
P
STOP
condition
P
STOP
condition
data 1 valid
002aac495
A0 R/W
002aac472
10 of 30