MAX2066ETL+ Maxim Integrated Products, MAX2066ETL+ Datasheet - Page 18

RF Amplifier 50-1000MHZ HI-LIN PARALLEL-CONTRD DIG

MAX2066ETL+

Manufacturer Part Number
MAX2066ETL+
Description
RF Amplifier 50-1000MHZ HI-LIN PARALLEL-CONTRD DIG
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX2066ETL+

Bandwidth
1000 MHz
Mounting Style
SMD/SMT
Operating Supply Voltage
5 V
Supply Current
70 mA
Maximum Power Dissipation
6.5 W
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Package / Case
TQFN-40
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
To capitalize on its fast 25ns switching capability, the
MAX2066 offers a supplemental 5-bit parallel control
interface. The digital logic attenuator-control pins
(D0–D4) enable the attenuator stages (Table 3).
Direct access to this 5-bit bus enables the user to avoid
any programming delays associated with the SPI
interface. One of the limitations of any SPI bus is the
speed at which commands can be clocked into each
peripheral device. By offering direct access to the 5-bit
parallel interface, the user can quickly shift between
digital attenuator states as needed for critical “fast-
attack” automatic gain-control (AGC) applications.
The MAX2066 has an added feature that provides
“rapid-fire” gain selection between four prepro-
Table 2. SPI Data Format (continued)
Table 3. Digital Attenuator Settings (Parallel Control)
18
Reserved
______________________________________________________________________________________
INPUT
FUNCTION
D0
D1
D2
D3
D4
Using the Parallel Control Bus
Disable 1dB attenuator, or when SPI is default programmer
Disable 2dB attenuator, or when SPI is default programmer
Disable 4dB attenuator, or when SPI is default programmer
Disable 8dB attenuator, or when SPI is default programmer
Disable 16dB attenuator, or when SPI is default programmer
“Rapid-Fire” Preprogrammed
Digital Attenuator Settings
D0 (LSB)
BIT
D7
D6
D5
D4
D3
D2
D1
Attenuation States
LOGIC = 0 (OR GROUND)
Bits D[7:0] are reserved. Set to logic 0.
grammed attenuation steps. As with the supplemental
5-bit bus mentioned above, this “rapid-fire” gain selec-
tion allows the user to quickly access any one of four
customized digital attenuation states without incurring
the delays associated with reprogramming the device
through the SPI bus.
The switching speed is comparable to that achieved
using the supplemental 5-bit parallel bus. However, by
employing this specific feature, the digital attenuator
I/O is further reduced by a factor of either 5 or 2.5 (5
control bits vs. 1 or 2, respectively) depending on the
number of states desired.
The user can employ the STATE_A and STATE_B logic-
input pins to apply each step as required (Table 4).
Toggling just the STATE_A pin (one control bit) yields
two preprogrammed attenuation states; toggling both
the STATE_A and STATE_B pins together (two control
bits) yields four preprogrammed attenuation states.
DESCRIPTION
Enable 1dB attenuator
Enable 2dB attenuator
Enable 4dB attenuator
Enable 8dB attenuator
Enable 16dB attenuator
LOGIC = 1

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