SI3015-FS Silicon Laboratories Inc, SI3015-FS Datasheet - Page 26

• Manufacturer Part Number: SI3015-FS
• Description: SI2400 ISOMODEM LINE-SIDE
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3015-FS

• Data Format: V.90
• Interface: Serial
• Voltage - Supply: 3.3 V ~ 5 V
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Baud Rates: -

Si2400
390 Hz) and waits to detect a 1300 Hz carrier for
220 ms. If the Si2400 detects more than 40 ms of a
1300 Hz carrier in a time window of 220 ms, then it will
set the ALERT pin (GPIO4) and the next character
echoed by the Si2400 will be a “v”.
If the Si2400 does not detect more than 40 ms of the
1300 Hz carrier in a time window of 220 ms, then it
reverses again and waits to detect a 390 Hz carrier for
220 ms. Then, if the Si2400 detects more than 40 ms of
a 390 Hz carrier in a time window of 220 ms, it will set
the ALERT pin (GPIO4) and the next character echoed
by the Si2400 will be a “c”.
At this point, if the Si2400 does not detect more than
40 ms of the 390 Hz carrier in a time window of 220 ms,
then it will hang up, set the ALERT pin (GPIO4), and the
next character echoed by the Si2400 will be an “N” (no
carrier).
Successful completion of a turnaround procedure in
either master or slave will automatically update
S07[4] (V23T) and S07[5] (V23R) to indicate the new
status of the V.23 connection.
In order to avoid using the ALERT pin, the host may
also be notified of the ALERT condition by using 9-bit
data
S0C[3] (9BF) = 0b will configure the ninth bit on the
Si2400 TXD path to function exactly as the ALERT pin
has been described.
V.42 HDLC Mode
The Si2400 supports V.42 through hardware HDLC
framing in all modem data modes. Frame packing and
unpacking,
generation and detection, CRC computation and
checking, zero insertion and deletion, and modem data
transmission and reception are all performed by the
Si2400. V.42 error correction and V.42bis data
compression must be performed by the host.
The digital link interface in this mode uses the same
UART interface (8-Bit Data and 9-Bit Data formats) as in
the asynchronous modes and the ninth data bit may be
used as an escape by setting S15[0] (NBE) = 1b. When
using HDLC in 9-Bit Data mode, if the ninth bit is not
used as an escape, it is ignored.
To use the HDLC feature on the Si2400, the host must
first
S07[7] (HDEN) = 1b. Next, the host may initiate the call
or answer the call using either the “ATDT#”, the “ATA”
command, or the auto-answer mode. (The auto-answer
mode is implemented by setting register S00 (NR) to a
non-zero value.) When the call is connected, a “c”, “d”,
or a “v” is echoed to the host controller. The host may
now send/receive data across the UART using either
26
enable
mode.
including
Setting
HDLC
opening
operation
S15[0] (NBE) = 1b
and
closing
by
setting
and
flag
Rev. 1.1
the 8-Bit Data or 9-Bit Data formats with flow control.
At this point, the Si2400 will begin framing data into the
HDLC format. On the transmit side, if no data is
available from the host, the HDLC flag pattern is sent
repeatedly. When data is available, the Si2400
computes the CRC code throughout the frame and the
data is sent with the HDLC zero-bit insertion algorithm.
HDLC flow control operates in a similar manner to
normal asynchronous flow control across the UART and
is shown in Figure 11. In order to operate flow control
(using the CTS pin to indicate when the Si2400 is ready
to accept a character), a DTE rate higher than the line
rate should be selected. The method of transmitting
HDLC frames is as follows:
1. After the call is connected, the host should begin sending
2. When the frame is complete, the host should simply stop
3. When the Si2400 is ready to send the next byte, if it has
4. After transmitting the first stop flag, the Si2400 will lower
The method of receiving HDLC frames is as follows:
1. After the call is connected, the Si2400 searches for flag
2. When the Si2400 detects the stop flag, it will send the last
the frame data to the Si2400, using the CTS flow control to
ensure data synchronicity. A 1-deep character FIFO is
implemented in the Si2400 to ensure that data is always
available to transmit.
sending data to the Si2400. As shown in Figure 11B, since
the Si2400 does not yet recognize the end-of-frame, it will
expect an extra byte and assert CTS. If CTS is used to
cause a host interrupt, then this final interrupt should be
ignored by the host.
not yet received any data from the host, it will recognize
this as an end-of-frame, raise CTS, calculate the final CRC
code, transmit the code, and begin transmitting stop flags.
CTS indicating that it is ready to receive the next frame
from the host. At this point the process repeats as in
step 1.
data. Then, once the first non-flag word is detected, the
CRC is continuously computed, and the data is sent
across the UART (8-Bit Data or 9-Bit Data mode) to the
host after removing the HDLC zero-bit insertion. The DTE
rate of the host must be at least as high as that of data
transmission. HDLC mode only works with 8-bit data
words; the ninth bit is used only for escape on TXD and
End-of-Frame Received (EOFR) on RXD.
data word in the frame as well as the two CRC bytes and
determine if the CRC checksum matches. Thus, the last
two bytes are not frame data, but are the CRC bytes,
which can be discarded by the host. If the checksum
matches, then the Si2400 echoes “G” (good). If the
checksum does not match, the Si2400 echoes “e” (error).
Additionally, if the Si2400 detects an abort (seven or more
contiguous ones), then it will echo an “A”.
When the “G”, “e”, or “A” (referred to as a frame result
word) is sent, the Si2400 raises the EOFR (end of frame
receive) pin (see Figure 10B). The GPIO1 pin must be