73M1903-IVTR/F Maxim Integrated Products, 73M1903-IVTR/F Datasheet - Page 5

• Manufacturer Part Number: 73M1903-IVTR/F
• Description: IC MODEM AFE V.22BIS 20-TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of 73M1903-IVTR/F

• Number Of Channels: 2
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Package / Case: 20-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Number Of Bits: -

1.1
peripheral to the DSP (host controller), the 73M1903 is the master of the serial port. It generates a serial
bit clock, Sclk, from a system clock, Sysclk, which is normally an output from an on-chip PLL that is
programmed by the user. The serial bit clock is derived by dividing the system clock by 18. The sclk rate,
Fsclk, is related to the frame synchronization rate, Fs, by the relationship Fsclk = 256 x Fs or Fs = Fsclk /
256 = Fsys / 18 / 256 = Fsys / 4608, where Fsys is the frequency of Sysclk. Fs is also the rate at which
both the transmit and receive data bytes are sent (received) to (by) the Host. Throughout this document
two pairs of sample rates, Fs, and crystal frequency, Fxtal, will be often cited to facilitate discussions.
They are:
DS_1903_032
The serial data port is a bi-directional port that is supported by many DSPs. Although the 73M1903 is a
1. Fxtal
2. Fxtal
3. Fxtal
Upon reset, until a switch to the PLL based clock, Pllclk, occurs, the system clock will be at the crystal
frequency, Fxtal, and therefore the serial bit clock will be Sclk = Fsys/18 = Fxtal/18.
Examples:
1. If Fxtal
2. If Fxtal
3. If Fxtal
When 73M1903 is programmed through the serial port to a desired Fs and the PLL has settled out, the
system clock will transition to the PLL-based clock in a glitch-less manner.
Examples:
1. If Fs
2. If Fs
3. If Fs
This transition is entirely controlled by the host. Upon reset or power down of PLL and/or analog front
end, the chip will automatically run off the crystal until the host forces the transition by setting a bit in a
designated serial port register – location bit 7, 0Eh. The transition is forced on or after the second Frame
Synch period following the write to a designated PLL programming register (0Dh).
When reprogramming the PLL the host should first transition the system clock to the crystal before
reprogramming the PLL so that any transients associated with it will not adversely impact the serial port
communication.
Power saving is accomplished by disabling the analog front end by clearing bit 7 of CTRL1 (address 00h),
ENFE=0.
During the normal operation, a data FS is generated by the 73M1903 at the rate of Fs. For every data FS
there are 16 bits transmitted and 16 bits received. The frame synchronization (FS) signal is pin
programmable for type. FS can either be early or late determined by the state of the TYPE input pin.
When the TYPE pin is left open, an early FS is generated in the bit clock prior to the first data bit
transmitted or received. When held low, a late FS operates as a chip select; the FS signal is active for all
bits that are transmitted or received. The TYPE input pin is sampled when the reset pin is active (low)
and ignored at all other times. The final state of the TYPE pin as the reset pin is de-asserted determines
the frame synchronization mode used.
Rev. 2.1
Serial Interface
1
2
3
1
2
3
= 7.2 kHz, Fsys = 4608 * Fs = 33.1776 MHz and sclk = Fsys / 18 = 1.8432 MHz.
= 8.0 kHz, Fsys = 4608 * Fs = 36.8640 MHz and sclk = Fsys / 18 = 2.048 MHz.
= 9.6 kHz, Fsys = 4608 * Fs = 44.2368 MHz and sclk = Fsys / 18 = 2.4576 MHz.
= 27 MHz, Fs
= 18.432 MHz, Fs
= 24.576 MHz, Fs
1
2
3
= 27.000 MHz, then sclk=1.500 MHz and Fs=sclk/256 = 5.859375 kHz.
= 18.432 MHz, then sclk=1.024 MHz and Fs=sclk/256 = 4.00 kHz.
= 24.576 MHz, then sclk=1.3653 MHz and Fs=sclk/256 = 5.33 kHz.
1
= 7.2 kHz
2
3
= 8 kHz.
= 9.6 kHz – chip default.
73M1903 Data Sheet
5