SST25VF020-20-4I-SAE Microchip Technology, SST25VF020-20-4I-SAE Datasheet - Page 9

• Manufacturer Part Number: SST25VF020-20-4I-SAE
• Description: IC FLASH MPF 2MBIT 20NS 8SOIC
• Manufacturer: Microchip Technology

Specifications of SST25VF020-20-4I-SAE

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 2M (256K x 8)
• Speed: 20MHz
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

2 Mbit SPI Serial Flash
SST25VF020
Read
The Read instruction outputs the data starting from the
specified address location. The data output stream is con-
tinuous through all addresses until terminated by a low to
high transition on CE#. The internal address pointer will
automatically increment until the highest memory address
is reached. Once the highest memory address is reached,
the address pointer will automatically increment to the
beginning (wrap-around) of the address space, i.e. for
Byte-Program
The Byte-Program instruction programs the bits in the
selected byte to the desired data. The selected byte must
be in the erased state (FFH) when initiating a Program
operation. A Byte-Program instruction applied to a pro-
tected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN)
instruction must be executed. CE# must remain active low
for the duration of the Byte-Program instruction. The Byte-
©2006 Silicon Storage Technology, Inc.
FIGURE 5: R
FIGURE 6: Byte-Program Sequence
SCK
CE#
SO
SI
MODE 3
MODE 0
EAD
MSB
0 1 2 3 4 5 6 7 8
S
EQUENCE
SCK
CE#
SO
SI
03
MODE 3
MODE 0
HIGH IMPEDANCE
MSB
0 1 2 3 4 5 6 7 8
MSB
ADD.
02
15 16
ADD.
HIGH IMPEDANCE
23 24
MSB
9
ADD.
ADD.
2 Mbit density, once the data from address location
3FFFFH had been read, the next output will be from
address location 00000H.
The Read instruction is initiated by executing an 8-bit com-
mand, 03H, followed by address bits [A
remain active low for the duration of the Read cycle. See
Figure 5 for the Read sequence.
Program instruction is initiated by executing an 8-bit com-
mand, 02H, followed by address bits [A
address, the data is input in order from MSB (bit 7) to LSB
(bit 0). CE# must be driven high before the instruction is
executed. The user may poll the Busy bit in the software
status register or wait T
self-timed Byte-Program operation. See Figure 6 for the
Byte-Program sequence.
MSB
31 32
15 16
D
ADD.
OUT
N
39 40
23 24
D
N+1
OUT
ADD.
47 48
31 32
MSB
D
N+2
OUT
BP
D
1231 F05.1
IN
LSB
for the completion of the internal
55 56
39
D
N+3
OUT
63 64
23
D
N+4
1231 F04.1
S71231-07-000
OUT
-A
23
0
-A
]. Following the
70
0
]. CE# must
Data Sheet
10/06