SI4030-B1-FMR Silicon Laboratories Inc, SI4030-B1-FMR Datasheet - Page 35

• Manufacturer Part Number: SI4030-B1-FMR
• Description: IC TX 900-960MHZ -8-13DB 20VQFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4030-B1-FMR

• Frequency: 900MHz ~ 960MHz
• Applications: General Purpose
• Modulation Or Protocol: FSK, GFSK, OOK
• Data Rate - Maximum: 256 kbps
• Power - Output: 13dBm
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -

The TX FIFO may be cleared or reset with the ffclrtx bit in “Register 08h. Operating Mode and Function Control 2.”
All interrupts may be enabled by setting the Interrupt Enabled bits in "Register 05h. Interrupt Enable 1" and
“Register 06h. Interrupt Enable 2,” on page 59. If the interrupts are not enabled the function will not generate an
interrupt on the nIRQ pin but the bits will still be read correctly in the Interrupt Status registers.
6.2. Packet Configuration
When using the FIFO, automatic packet handling may be enabled for the TX mode. "Register 30h. Data Access
Control" through “Register 3Eh. Packet Length,” on page 79 control the configuration for Packet Handling. The
usual fields for network communication (such as preamble, synchronization word, headers, packet length, and
CRC) can be configured to be automatically added to the data payload. The fields needed for packet generation
normally change infrequently and can therefore be stored in registers. Automatically adding these fields to the data
payload greatly reduces the amount of communication between the microcontroller and the Si4030/31/32 and
reduces the required computational power of the microcontroller.
The general packet structure is shown in Figure 12. The length of each field is shown below the field. The preamble
pattern is always a series of alternating ones and zeroes, starting with a zero. All the fields have programmable
lengths to accommodate different applications. The most common CRC polynominals are available for selection.
An overview of the packet handler configuration registers is shown in Table 12.
6.3. Packet Handler TX Mode
If the TX packet length is set the packet handler will send the number of bytes in the packet length field before
returning to IDLE mode and asserting the packet sent interrupt. To resume sending data from the FIFO the
microcontroller needs to command the chip to re-enter TX mode. Figure 14 provides an example transaction where
the packet length is set to three bytes.
Add R/W Function/D
7C
7D
08
R/W
R/W
R/W
1-512 Bytes
Preamble
escription
Operating &
Control 2
Control 1
Control 2
Function
TX FIFO
TX FIFO
1-4 Bytes
Reserved Reserved Reserved Reserved
Reserved Reserved txafthr[5]
Reserved Reserved txaethr[5] txaethr[4] txaethr[3] txaethr[2] txaethr[1] txaethr[0]
D7
D6
Figure 12. Packet Structure
D5
Rev 1.1
txafthr[4]
D4
Data
txafthr[3] txafthr[2] txafthr[1] txafthr[0]
autotx
D3
Reserved Reserved
Si4030/31/32-B1
D2
D1
Bytes
0 or 2
CRC
ffclrtx
D0
POR Def.
00h
37h
04h
35