ATA6286N-PNPW Atmel, ATA6286N-PNPW Datasheet - Page 11

• Manufacturer Part Number: ATA6286N-PNPW
• Description: IC CTRL/XMITTER 433MHZ 32-VQFN
• Manufacturer: Atmel

Specifications of ATA6286N-PNPW

• Frequency: 433MHz
• Applications: TPM (Tire Pressure Monitor)
• Modulation Or Protocol: ASK, FSK
• Data Rate - Maximum: 20 kbps
• Power - Output: 6dBm
• Current - Transmitting: 8.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 9
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Lead Free Status / Rohs Status: Details

4.4
4.5
4958BS–AUTO–01/09
General Description
Functional Description
This fully integrated PLL transmitter allows the design of simple, low-cost RF miniature transmit-
ters for TPM and RKE applications. The VCO is locked to 24
ATA6285N/ATA6286N. Thus, a 13.125 MHz/13.56 MHz crystal is needed for a 315 MHz/
433.92 MHz transmitter. All other PLL and VCO peripheral elements are integrated.
The XTO is a series resonance (current mode) oscillator. Only one capacitor and a crystal con-
nected in series to GND are needed as external elements in an ASK system. The internal FSK
switch, together with a second capacitor, can be used for FSK modulation. The crystal oscillator
needs typically 0.6 ms until the CLK output is activated if a crystal as defined in the electrical
characteristics is used (e.g., TPM crystal). For most crystals used in RKE systems, a shorter
time will result.
The CLK output is switched on if the amplitude of the current flowing through the crystal has
reached 35% to 80% of its final value. This is synchronized with the 1.64 MHz/1.69 MHz CLK
output. As a result, the first period of the CLK output is always a full period. The PLL is then
locked < 250 µs after CLK output activation. This means an additional wait time of
necessary before the PA can be switched on and the data transmission can start. This results in
a significantly lower time of about 0.85 ms between enabling the ATA6285N/ATA6286N and the
beginning of the data transmission which saves battery power especially in tire pressure moni-
toring systems.
The power amplifier is an open-collector output delivering a current pulse which is nearly inde-
pendent from the load impedance and therefore the output power can be controlled via the
connected load impedance.
This output configuration enables a simple matching to any kind of antenna or to 50 . A high
power efficiency for the power amplifier results if an optimized load impedance of
Z
433.92 MHz is used at the 3V supply voltage.
If ASK = Low, FSK = Low and ENABLE = open or Low, the circuit is in power-down mode con-
suming only a very small amount of current so that a lithium cell used as power supply can work
for many years.
If the ENABLE pin is left open, ENABLE is the logical OR operation of the ASK and FSK input
pins. This means, the IC can be switched on by either the FSK of the ASK input.
If the ENABLE pin is Low and ASK or FSK are High, the IC is in idle mode where the PLL, XTO
and power amplifier are off and the microcontroller ports controlling the ASK and FSK inputs can
be used to control other devices. This can help to save ports on the microcontroller in systems
where other devices with 3-wire interface are used.
With FSK = High and ASK = Low and ENABLE = open or High, the PLL and the XTO are
switched on and the power amplifier is off. When the amplitude of the current through the crystal
has reached 35% to 80% of its final amplitude, the CLK driver is automatically activated. The
CLK output stays Low until the CLK driver has been activated. The driver is activated synchro-
nously with the CLK output frequency, hence, the first pulse on the CLK output is a complete
period. The PLL is then locked within < 250 µs after the CLK driver has been activated, and the
transmitter is then ready for data transmission.
Load, opt
= 380 + j340 (ATA6285N) at 315 MHz and Z
ATA6285N/ATA6286N [Preliminary]
Load, opt
= 280 + j310 (ATA6286N) at
f
X T A L
/32 x f
250 µs is
X T A L
for
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