SI4010-B1-GS Silicon Laboratories Inc, SI4010-B1-GS Datasheet - Page 90

• Manufacturer Part Number: SI4010-B1-GS
• Description: IC TX 27-960MHZ FSK 3.6V 14SOIC
• Manufacturer: Silicon Laboratories Inc
• Series: EZRadio®r
• Type: ISM Transmitterr

Specifications of SI4010-B1-GS

• Package / Case: 14-SOIC (0.154", 3.90mm Width)
• Frequency: 27MHz ~ 960MHz
• Applications: Garage Openers, RKE, Security Alarms
• Modulation Or Protocol: FSK, OOK
• Data Rate - Maximum: 100 kBaud
• Power - Output: 10dBm
• Current - Transmitting: 19.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 4kB RAM
• Features: 8051 MCU Core, Crystal-less Operation
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 27 MHz to 960 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V to 3.6 V
• Supply Current: 10 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 336-1974-5

*Notes: Bit addressable registers.
Si4010
24. On-Chip Registers
There are two register regions on chip:


24.1. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the Si4010's resources and peripherals. The
CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well as implementing
additional SFRs used to configure and access the sub-systems unique to the Si4010. This allows the addi-
tion of new functionality while retaining compatibility with the MCS-51™ instruction set. Table 24.2 lists the
SFRs implemented in the Si4010 device family.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, P1, ACC, IE, etc.) are bit-address-
able as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the
SFR space are reserved for future use. Accessing these areas will have an indeterminate effect and
should be avoided. Refer to the corresponding pages of the data sheet, as indicated in Table 24.2, for a
detailed description of each register.
90
0*
8*
A
B
C
D
E
1
2
3
4
5
6
7
9
F
Special Function Registers region
XREG region
CLKOUT_SET
GFM_CONST
SBOX_DATA
GFM_DATA
PCON
0X80
DPH
DPL
P0*
SP
FC_INTERVAL ODS_RATEH
RBIT_DATA
RTC_CTRL
Table 24.1. Special Function Register (SFR) Memory Map
FC_CTRL
0x90
P1*
ODS_WARMS2 INT_FLAGS
ODS_WARM1
ODS_TIMING
ODS_RATEL
ODS_CTRL
ODS_DATA
P0CON
P1CON
0xA0
P2*
IE*
PORT_INTCFG
PORT_CTRL
GPR_CTRL
GPR_DATA
PORT_SET
TMR3CTRL TMR_CLKSEL
Rev. 0.5
TMR3RH
SYSGEN
TMR3RL
TMR3H
TMR3L
0xB0
IP*
TMR2CTRL*
TMR2RH
TMR2RL
TMR2H
PA_LVL
TMR2L
0xC0
BOOT_FLAGS
PROT0_CTRL
PSW*
0xD0
SYS_SET
LC_FSK
ACC*
0xE0
EIE1
0xF0
EIP1
B*