HSP50210JI-52Z Intersil, HSP50210JI-52Z Datasheet - Page 17

• Manufacturer Part Number: HSP50210JI-52Z
• Description: IC DEMODULATOR COSTAS 84-PLCC
• Manufacturer: Intersil

Specifications of HSP50210JI-52Z

• Function: Demodulator
• Frequency: 52MHz
• Rf Type: AM, FM
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Sampling Error Detector
The Sampling Error Detector is a decision based error
detector which determines sampling errors on both the I and
Q processing paths. The detector assumes that it is fed with
samples of the baseband waveform taken in the middle of
the symbol period (mid-symbol sample) and between
symbols (end-symbol sample) as shown in Figure 12. The
sampling error is a measure of how far the mid-symbol
sample is from the symbol transition mid-point. The
transition mid-point is half way between two symbol
decisions. The detector makes symbol decisions by
comparing the end-symbol samples against a selectable
threshold set (see Modulation Order Select bits 9 through 10
in Table 29 on page 37). The error term is generated by
subtracting the mid-symbol sample from the transition mid-
point. The sign of the error term is negated for negatively
sloped symbol transitions. If no symbol transitions are
detected the error detector output is zeroed. Errors on both
the I and Q processing paths are summed and divided by
two if Double Rail error detection is selected (see Symbol
Tracking Configuration Control Register, Bit 8: Table 29 on
page 37).
The sampling Error Detector provides an error accumulator
to compensate for the processing rate of the loop filter. The
error detector generates outputs at the symbol rate, but the
loop filter can only accept inputs every eight f
Thus, if the symbol rate is faster than 1/8 CLK, the error
accumulator should be used to accumulate the error until the
loop filter is ready for a new input. If the error accumulator is
not used when the symbol rate exceeds 1/8 CLK, some error
outputs will be missed. For example, if f
error accumulation is required for symbol rates greater than
5 MSPS (f
be scaled accordingly if the accumulator is used.
SAMPLING
FIGURE 12. TRACKING ERROR ASSOCIATED WITH
ERROR
MID-SYMBOL
CLK
SAMPLE
BASEBAND SAMPLING ON EITHER I OR Q RAIL
(BPSK/QPSK)
/8). Note: The loop filter lead gain term must
X
TRANSITION
MIDPOINT
17
X
CLK
X
END-SYMBOL
SAMPLE
= 40MHz, then
CLK
clocks.
EXPECTED
SYMBOL
LEVELS
HSP50210
Symbol Tracking Loop Filter
The Symbol Tracking Loop Filter is a second order lead/lag
filter. The sampling error is weighted by the lag gain and
accumulated to give the integral response (see Figure 11).
The Lag Accumulator output is summed with the sampling
error weighted by the Lead Gain. The result is a frequency
term which is output serially, via the SOF output, to the
NCO/VCO controlling the baseband sample rate (see “Serial
Output Interfaces” on page 23). In basic configurations, the
SOF output of the HSP50210 is connected to the SOF input of
the HSP50110.
Two sets of registers are provided to store the loop gain
parameters associated with acquisition and tracking. The
appropriate loop gain parameters are selected manually via
the Microprocessor Interface or automatically via the Carrier
Lock Detector. The loop filter’s lead and lag gain terms are
represented as a mantissa and exponent. The mantissa is a
4-bit value which weights the loop filter input from 1.0 to
1.9375. The exponent defines a shift factor that provides
additional weighting from 2
mantissa and exponent provide a gain range between 2
and
Lead/Lag Gain = (1.0+M*2
where M = a 4-bit binary number from 0 to 15, and E is a 5-bit
binary value ranging from 0 to 31. For example, if M = 0101
and E = 00110, the Gain = 1.3125*2
Control Registers described in Tables 32 and 33 beginning on
page 38.
A limiter is provided on the lag accumulator output to keep the
baseband sample rate within a user defined range (see
Tables 30 and 31 on page 38). If the lag accumulator exceeds
either the upper or lower limit, the accumulator is loaded with
the limit. For additional loop filter control, the loop filter output
can be frozen by asserting the FZ_ST pin which null the
sampling error term into the loop filter. The lag accumulator
can be initialized to a particular value and can be read via the
microprocessor interface as described in “Reading from the
Microprocessor Interface” on page 27, and Table 34 on
page 39. The symbol tracking loop filter bit weighting is
identical to the carrier tracking loop bit weighting, shown in
Figures 9 and 10.
Soft Decision Slicer
The Soft Decision Slicer encodes the I/Q end-symbol
samples into 3-bit soft decisions. The input to the slicer is
assumed to be a bipolar (2ary) baseband signal
representing encoded values of either ‘1’ or ‘0’. The most
significant bit of the 3-bit soft decision represents a hard
decision with respect to the mid-point between the expected
symbol values. The 2 LSBs represent a level of confidence
in the decision. They are determined by comparing the
magnitude of the slicer input to multiples (1x, 2x, and 3x) of a
programmable soft decision threshold (see Figure 13).
~
1.0 as given by Equation 10.
-4
-1
)*2
to 2
-(32 -E)
-32
-26
. Together the loop gain
. They are stored in the
(EQ. 10)
July 2, 2008
FN3652.5
-32