ISL5239KIZ Intersil, ISL5239KIZ Datasheet
ISL5239KIZ
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ISL5239KIZ Summary of contents
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... PART NUMBER MARKING ISL5239KI ISL5239KI ISL5239KIZ ISL5239KIZ (Note) ISL5239EVAL1 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil ...
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Block Diagram CLK TRIGIN IIN<17:0> INPUT PRE-DISTORTER FORMATTER WITH QIN<17:0> AND TWO CLKOUT INTERPOLATOR LUTs X1, X2, X4, X8 ISTRB TRIGOUT A<5:0> INPUT P<15:0> MEMORY CS uP INTERFACE ( BUSY RESET 2 ISL5239 ...
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Functional Block Diagram ISL5239 Pre-Distortion Linearizer IIN<17:0> OFFSET BYPASS BYPASS BINARY QIN<17:0> HALF BAND CLKOUT FILTER / DE-MUX / ISTRB INPUT TYPE (PAR/SERIAL) TMS TDI TCK JTAG TRST TDO TRIGIN PD MAG. THRESHOLD MAX COMPARE MIN uP ...
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Pinout VCCC IIN16 B ISTRB NC IIN17 VCCC RD F VCCIO P10 P12 VCCIO J CLK GND RESET ...
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Pin Descriptions (Continued) NAME TYPE A<5:0> I 6-bit address bus that operates with P<15:0>, CS, RD, and WR to write to and read from the devices internal control registers. Bit 5 is the MSB. Chip Select. (active low). Enables device ...
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Functional Description The ISL5239 is a full-featured digital pre-distortion part featuring a high-performance lookup-table based pre- distortion (PD) processing unit. It includes an interpolator for upsampling and supports all varieties of upconversion architectures with a programmable correction filter for equalization ...
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HALFBAND FILTER 2 RESPONSE 0 -20 -40 -60 -80 -100 -120 -140 0 0.1 0.2 0.3 0.4 0.5 0.6 NORMALIZED FREQUENCY (NYQUIST=1) FIGURE 3A. X4, HB1 AND HB2 ENABLED FREQUENCY RESPONSE HALFBAND FILTER 3 RESPONSE 0 -20 -40 -60 -80 ...
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The pre-distorter block diagram is shown in Figure 4. FROM I IFIP TEST Q LUT ADDRESS CALCULATION TEST FUNC. SEL. OFFSET SCALE PD MAG. POWER LUT DATA I ADDR LUT DATA Q LUT DELTA DATA I ...
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The IF converter frequency response is as shown in Figure 7, with the folding effect shown in Figure 7A for the x2, Fs/4 upconverter case. IFC FILTER RESPONSE (x2 MODE) 0 -20 -40 -60 -80 -100 -120 -140 0 0.1 ...
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I and Q channels. Typical implementation is as shown in Figure 10. FIGURE 11. IMBALANCE CORRECTION The Output formatter also provides DC offset correction to 1/4 LSB for 18-bit outputs to reduce analog DC offsets ...
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For the input data, the 0x04, bit 3 input data round bit must also be selected and the feedback memory length count is always set to 1024. To invoke memory operation, the 0x07, bit 4 feedback memory mode or bits ...
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General Comments About Modes Once a trigger is detected in the ARMED condition, all following triggers are ignored during the sequence. The system does not acknowledge new triggers until a new transaction is invoked and re-armed. When a new mode ...
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The address map and bit field details for the microprocessor interface is shown in the Tables 2-48. The procedures for reading and writing to this interface are provided below. Microprocessor Read/Write Procedure The ISL5239 offers the user microprocessor read/write access ...
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Read Access to the Capture Memory 1. Perform a direct write to control word 0x04 by setting up the address on A<5:0>, data on P<15:0>, and generating a rising edge on WR. 0x04 selects the auto increment mode and the ...
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Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . +2.5VCCC, 4.6V VCCIO Input, Output or I/O Voltage . . . . . ...
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AC Electrical Specifications PARAMETER CLK Frequency CLK Period CLK High, FBCLK High CLK Low, FBCLK Low Setup Time RESET High to CLK (Note 8) Hold RESET High from CLK RESET Low Pulse Width (Note 7) Setup Time P<15:0> ...
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AC Electrical Specifications PARAMETER Hold Time SERIN from CLK (Note 7) Delay Time from CLK to TRIGOUT Setup Time from TRIGIN to CLK Hold Time TRIGIN from CLK Setup Time from TMS and TDI to TCK Hold Time TMS and ...
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Waveforms (Continued) CLK t DS IN<17:0>, VALID QIN<17:0>, ISTRB CCO1 CCON CLKOUT t PDC1 IOUT<19:0>, VALID VALID QOUT<19:0> FIGURE 17. INPUT/OUTPUT TIMING CLK t CFBD FBCLK FB<19:0> FIGURE 19. FEEDBACK TIMING CLK RD ...
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Programming Information and Device Control Registers ADDRESS (5:0) TYPE 00 R/W Global R/W Input Formatter and Interpolator R/W Capture Memory 05 R/W 06 R/W 07 R/W 08 R/W 09 R/W 0a R/W 0b R/W ...
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ADDRESS (5:0) TYPE FUNCTION 30 R/W Output Data Conditioner 31 R/W 32 R/W 33 R/W 34 R/W 35 R/W 36 R/W 37 R BIT FUNCTION 15:11 Reserved Not Used 10:8 ID Index Pointer that selects a ...
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TYPE: INPUT FORMATTER AND INTERPOLATOR, ADDRESS: 0x02 BIT FUNCTION 15 Reserved Not used. 14 Clear Status Set high to clear all status bits, set low (default) to allow the status bits to update. 13:8 Reserved Internal use only. 7 Reserved ...
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BIT FUNCTION 15:14 Reserved Not used. 13 Address Auto Increment When set high, automatically increments the memory address after any access operation (read or write). 12 Memory Select Selects the memory for access Input memory (default ...
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BIT FUNCTION 15:5 Reserved Not used. 4 Feedback Memory Mode Selects the feedback memory operating mode Idle. (default) Memory not operating Capture. Memory is capturing data in accordance with the mode and trigger settings specified ...
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BIT FUNCTION 15:0 Memory Data <15:0> Lower 16 bits of capture memory data word. BIT FUNCTION 15:0 Memory Data <31:16> Higher 16 bits of capture memory data word. Writing to this address triggers the write to the memory and increments ...
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BIT FUNCTION 15:14 Reserved Not used 13:12 Magnitude Function Selects the magnitude calculation function as: Select 00 - Log. Log base 2 of magnitude squared computed as log2 Linear. Linear magnitude computed as sqrt ( Power. ...
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BIT FUNCTION 15:0 LUT Data I Real distortion data written to or read back from LUT. Selectable as (-0.5...(0.5-increment)) in increments - BIT FUNCTION 15:13 Reserved Not used. 12 Serial Output Enable Set to high to enable the ...
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BIT FUNCTION 15:1 Reserved Not used. 0 Reserved Internal use only. BIT FUNCTION 15:14 Reserved Not used. 13:12 Reserved Internal use only. 11:9 Reserved Not used. 8 Reserved Internal use only. 7:6 Reserved Not used. 5:4 IF Conv. Mode Selects ...
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BIT FUNCTION 15:8 Reserved Not used. 7:0 Coefficient Address Pointer to current LUT location. Default is 0. 0x00-0x7F are I coefficients, 0x80-0xff are Q coefficients. Master register to slave register transfer occurs after the processor interface last write to the ...
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TYPE: OUTPUT DATA CONDITIONER, ADDRESS: 0x31 BIT FUNCTION 15:0 hm Coefficient I-to-I (hm) coefficient values loaded from the master registers to the slave registers when the user writes the last coefficient register in control word 0x38. The slave registers are ...
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TYPE: OUTPUT DATA CONDITIONER, ADDRESS: 0x39 BIT FUNCTION 15:4 Reserved Not used. 3:2 Reserved Internal use only Channel Status When high indicates that the output data conditioner saturated at least one sample since the last control word 0x30, ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. How- ever, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries ...