SI4126M-EVB Silicon Laboratories Inc, SI4126M-EVB Datasheet - Page 3

• Manufacturer Part Number: SI4126M-EVB
• Description: BOARD EVALUATION FOR SI4126
• Manufacturer: Silicon Laboratories Inc
• Type: Synthesizerr

Specifications of SI4126M-EVB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SI4126
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1112

AUXOUT
The AUXOUT pin of the frequency synthesizer can be
programmed for a variety of functions. The evaluation
board is normally populated so that this pin can be read
by the PC for serial reads from the IC. Other functions
can be monitored on the AUXOUT test point as well.
Refer to the appropriate synthesizer data sheet for
details of AUXOUT’s functionality and configuration.
Hardware Power Down
The hardware power-down input, PWDNB, can be
driven several different ways on the evaluation board.
The default configuration is pulled high (enabled)
through a resistive pull-up, R21. This pin may be
controlled through an external source or via evaluation
software.
Function
Synthesizer and Reference
Clock Power
Reference Clock
PWDNB
Driven by external
reference clock
User-supplied
User-supplied
Driven by PC
Always high
generator
On-board
On-board
regulator
Option
Table 2. Jumper Settings
Preliminary Rev. 0.5
JP5: jumper TCXO to OFF
JP5: jumper TCXO to ON
JP4: jumper REG to 3 V
JP4: jumper UNREG to
JP6: TCXO to XIN
Jumper Settings
JP6: EXT to XIN
JP2: no jumper
JP3: no jumper
JP2: no jumper
JP2: jumper
JP3: jumper
JP3: jumper
To control PWDNB with an external generator, place a
shorting block on JP3. There should not be a shorting
block on JP2. Connect the output of the generator to
test point PWDNB. The test point labeled GND should
be connected to the shield of the cable.
The
synthesizer through the PWDNB pin. JP2 and JP3 must
both be jumpered to use this feature. The PWDNB test
point can then be used to monitor the PWDNB signal.
Refer to the appropriate synthesizer data sheet for a
complete explanation of software and hardware power
management options.
3 V
evaluation
Si4133/33G-EVB
software
No supply required on JP11 3 V pin
Check data sheet for requirements.
trigger to PWDNB/GND test points.
PWDNB provided by external gen-
software; Connect instrumentation
erator connected to PWDNB/GND
PWDNB controlled by evaluation
Supply required on JP11 3 V pin
Power-up/down controlled by
Clock signal required on J8;
No clock required on J8
register settings.
can
test points.
Notes
power
down
the
3