ATA555811C-DDB Atmel, ATA555811C-DDB Datasheet - Page 28

• Manufacturer Part Number: ATA555811C-DDB
• Description: IC IDIC 1KBIT R/W DIE
• Manufacturer: Atmel

Specifications of ATA555811C-DDB

• Function: Read/Write
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.4
28
Write Single Block
ATA5558
Table 7-5.
Table 7-6.
The Write Single Block command only effects tag(s) which have been previously been put in the
Selected state. It performs the programming of a specific block address with a 32-bit block of
data and associated lock bit. For password protected memory blocks the LoginWrite command
has to be executed first, otherwise the programming will fail and an error code will be returned.
Memory blocks which have a 1 in the lock bit are locked and cannot be written. The command
protocol includes downlink CRC (CRC_d) which is used to check the downlink address and
data. This CRC_d can be mandatory or optional depending on the state of bit 10 of the configu-
ration register. If set to 1, the CRC_d must always be included and correct for the data
programming to take place. If set to 0, the CRC_d is optional i.e. it is only checked if the CRC
data is present.
On receiving the Write command, and if necessary checking the CRC_d, the tag will start the
EEPROM programming sequence. The maximum EEPROM program time per block (including
the lock bit) is 6 ms. This programming cycle includes an automatic read verification phase
which makes sure that the data has been programmed securely thus ensuring satisfactory long
term data retention. To signal the completion of a successful programming cycle, the tag returns
a single SOF pattern.
If for any reason the programming of the data block fails, the tag will generate the corresponding
error code. The error code bits are dual pattern coded (see
ceded by a SOF pattern. An attempt to write to a locked block address or a downlink CRC error
causes an immediate abort of the programming cycle followed by the transmission of the corre-
sponding error response. In the case of an EEPROM data verification failure, the error response
is returned after the completion of the programming cycle.
Table 7-7.
Note:
Command
Write Single Block
= 00 01
4 bits
Command
Read = 00 01
4 bit
SOF
Start of Frame
3 .. 10-bit period
1. The downlink CRC (CRC_d) must be appended if bit 10 of the configuration register = 1, oth-
erwise it is optional.
Interrogator Command Parameters
Tag Response
Interrogator Command Parameters
Parameter 1
Start Block Address
6 bits (MSB first)
Multiple Data Blocks
((EndAddr – StartAddr + 1)
Data
(MSB first)
Parameter 1
Block Address
6 bits (MSB first)
Parameter 2
0 + Lock bit
2 bits
End Block Address
Parameter 2
6 bits (MSB first)
32) bits
Parameter 3
Write Data
32 bits (MSB first)
CRC
CRC_u (Start Block Addr +
End Block Addr + [CRC_d*] + Data)
16 bits (MSB first)
Figure 3-1 on page
CRC (optional)
CRC_d (Start Block Addr +
End Block Addr)
16 bits (MSB first)
CRC
CRC_d (Block Addr
+ Lock + Data)
16 bits (MSB first)
(1)
4681E–RFID–11/09
10) and pre-