ATA555812C-DDB Atmel, ATA555812C-DDB Datasheet - Page 12

• Manufacturer Part Number: ATA555812C-DDB
• Description: IC IDIC 1KBIT R/W DIE
• Manufacturer: Atmel

Specifications of ATA555812C-DDB

• Function: Read/Write
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.2.1
3.2.2
Table 3-1.
12
Parameter
Start gap
Write gap
Write data
coding (gap
separation)
Notes:
1. All absolute times assume T
2. All the above timing data is that which should appear on the device terminals so that the device can operate correctly.
ATA5558
Start Gap
4PPM Command Encoding
Depending on the coil used (e.g. Q factor etc.) and the transmission medium, the values implemented in the interrogator
could vary slightly.
Modified Pulse Position Modulation - Timing Parameters
Remark
Reference data 00
00 data
01 data
10 data
11 data
The first command gap is usually slightly longer (~20 field clocks) than the following data gaps.
This is referred to as the start gap. All interrogator to tag commands are initiated by such a start
gap. As soon as the clock extractor detects a start gap, the tag’s receive damping is switched
on. This serves to improve the gap detection of all following data gaps.
A start gap can be detected at any time after the completion of the tag’s power on reset delay
sequence (RF field-on plus ~3 ms). If a gap is received during this delay sequence, irrespective
of whether it is part of a command or a start gap, the delay will restarted. Commands or partial
command sequences occurring during the power on reset sequence will not executed.
The timing between data gaps depends on the Downlink Data Rate (DDR) in the configuration
register and is nominally 9 or 13 field clocks for a 00, 17 or 29 field clocks for a 01, 25 or 46 field
clocks for a 10 and 33 or 61 field clocks for a 11. The duration of the field gaps lie between 8 and
20 field clocks. Should no gap be detected for more than the maximum 11 gap separation (see
Table
release the receive damping. If an error is detected within the command sequence (e.g. incor-
rect number of bits received, CRC check failed etc.) the tag will return a dual pattern coded error
to the interrogator and ignore the command. The first two bits of every command constitute the
Start of Command (SOC) and is always 00. This SOC is used as a timing reference for all follow-
ing data (see
conditions.
3-1), the tag(s) will terminate the present command decoding mode and, if enabled
C
Symbol
S
W
d
d
d
d
d
ref
00
01
10
11
gap
= 1/f
gap
Table
C
= 8 µs (f
3-1), thus providing an auto-adjustment to allow for varying environmental
d
d
d
d
ref
ref
Min.
ref
ref
8
8
9
+ 13
+ 21
C
– 3
+ 5
Master Key = 6 or 9
= 125 kHz)
DDR = 1 and
d
d
d
ref
ref
Typ.
ref
d
10
10
–
+ 16
+ 24
ref
+ 8
d
d
d
d
ref
ref
ref
Max.
ref
50
20
68
+ 12
+ 20
+ 28
+ 4
d
d
d
d
ref
ref
Min.
ref
ref
13
8
8
+ 25
+ 41
– 7
+ 9
Master key
DDR = 0 or
d
d
d
ref
ref
ref
Typ.
d
10
10
–
+ 16
+ 32
+ 48
ref
6 or 9
d
d
d
d
ref
ref
ref
Max.
ref
50
20
72
+ 24
+ 40
+ 56
4681E–RFID–11/09
+ 8
Unit
T
T
T
T
T
T
T
c
c
c
c
c
c
c