AD6623S/PCB Analog Devices Inc, AD6623S/PCB Datasheet - Page 17

• Manufacturer Part Number: AD6623S/PCB
• Description: BOARD EVAL SGNL PROCESSOR AD6623
• Manufacturer: Analog Devices Inc

Specifications of AD6623S/PCB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD6623
• Lead Free Status / Rohs Status: Not Compliant

OVERVIEW OF THE RCF BLOCKS
The Serial Port passes data to the RCF with the appropriate format
and bit precision for each RCF configuration, see Figure 17. The
data may be modulated vectors or unmodulated bits. I and Q vectors
are sent directly to the Interpolating Fir Filter. Unmodulated
bits may be sent to the PSK Modulator, the Interpolating MSK
Modulator, or the Interpolating QPSK Modulator. The PSK
Modulator produces unfiltered I and Q vectors at the symbol rate
which are then passed through the Interpolating FIR Filter. The
Interpolating MSK Modulator and the Interpolating QPSK
Modulator produce oversampled, pulse-shaped vectors directly
without employing the Interpolating FIR Filter. When possible,
the MSK and QPSK modulators are recommended for increased
REV. A
Figure 17. Data Formats Supported by the AD6623 when SCLK Master (SCS = 0), and SFDO Set for Frame Request (SFE = 0)
Important notes: The sync pulse, s, should be held at Logic 1 for only one serial frame since every frame with Logic 1 in the s position will cause the RCF Scale Hold-off
Counter to reload its beginning count and begin counting again. The RCF Scale Hold-off Counter counts master CLK cycles. The REST time period is a programmable 5-bit
value that counts interpolated RCF output samples before resuming serial input to the channel. The succeeding actions of any hold-off counter in the AD6623 can be defeat-
ed by setting its count value to 0.
D1
D0
31
23
15
M
M
M
4
4
4
2
0
1
0
D1
D0
30
22
14
3
S
3
S
3
S
1
0
MSK/GSM
BIT
D1
D0
29
21
13
2
2
X
2
X
0
< MSB, I, LSB >
M = mode bit. If M = 0, then the MSB of 3-bit mode select word at 0xn0C:6 is set to 0 (this is also called MODE 0). If M = 1, then the MSB is set to 1 and this is
MODE 1. Mode allows quick format changes via the serial port, for example, 010 = GMSK and 110 = 3pi/8PSK. The value m should be held for the duration of the
time slot since the value of m will only be updated after the RCF Scale Holdoff Counter reaches a value of 1 (see below).
S = serial time slot sync bit. If S = 0, then no sync is generated. If S = 1, a “Serial Time Slot Sync” occurs that loads the RCF Scale Hold-off Counter with a user
programmed value and commences a backwards count of CLK cycles. When the counter reaches one, an automatic sequence occurs as follows: Power Ramp
Down occurs, m (above) is updated, serial input is suspended for a REST or QUIET time and any control register with a 2 superscript is updated. After REST, the
serial input becomes active and the power level is ramped up to the Fine Scale multiplier value or any lesser power level. Ramp enable bit, 0xn16:0, must be set
to logic 1 for the ramp functions to occur. See the RCF Power Ramping and Time Slot Synchronization sections for more detail.
X = don’t care
D = payload data bit
QPSK
BIT
D2
D1
28
20
12
1
1
1
X
8PSK
BIT
D0
D0
D0
27
19
11
0
0
0
< MSB, I, LSB >
26
18
10
MSK/GSM
QPSK
8PSK
BIT
BIT
BIT
25
17
9
< MSB, I, LSB >
24
16
8
These three formats are
available only when SERIAL
TIME SLOT SYNC ENABLE
cont. reg. 0xn16:2 = 0 and
ignored in FIR Mode
23
15
7
SERIAL SYNC
22
14
6
RAMP
21
13
< MSB, Q, LSB >
5
20
12
4
19
11
3
18
10
2
These three formats are
available only when SERIAL
TIME SLOT SYNC ENABLE
cont. reg. 0xn16:2 = 1 and
ignored in FIR Mode
17
9
1
16
8
0
15
7
< MSB, Q, LSB >
COMPACT FIR
–17–
14
6
BIT
throughput and decreased power consumption compared to
Interpolating FIR Filter. In addition, the Interpolating MSK
Modulator can realize filters with nonlinear inter-symbol inter-
ference, achieving excellent accuracy for GMSK applications.
After interpolation, an optional Allpass Phase Equalizer (APE)
can be inserted into the signal path. The APE can realize any real,
stable, two-pole, two-zero all-pass filter at the RCF’s interpolated
rate. This is especially useful to precompensate for nonlinear phase
responses of receive filters in terminals, as specified by IS-95.
When active, the APE utilizes shared hardware with the interpo-
lating modulators and filter, which may reduce the allowed RCF
throughput, inter-symbol interference, or both. See Figure 18.
13
5
12
4
11
3
10
2
< MSB, Q, LSB >
9
1
8
0
7
COMPACT FIR
6
BIT
5
4
3
2
1
0
AD6623
BIT
FIR