AD6620S/PCB Analog Devices Inc, AD6620S/PCB Datasheet - Page 17

• Manufacturer Part Number: AD6620S/PCB
• Description: BOARD EVAL DUAL RCVR W/AD6620AS
• Manufacturer: Analog Devices Inc

Specifications of AD6620S/PCB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD6620

If fractional rate input timing is necessary in the Diversity Chan-
nel Real Mode, the A/B pin must toggle at half the rate of the
A/D sample clock. The timing diagram below shows a 3× pro-
cessing clock. In this situation there will be one ADC encode
pulse for every three AD6620 CLK pulses and data must be
taken on every third CLK pulse. The CLK edges that corre-
spond to the latching of A and B channel data are shown in
Figure 26.
EXP[2:0]
IN[15:0]
EXP[2:0]
IN[15:0]
CLK
CLK
IF CLK 2x IS USED TO CLOCK THE AD6620, THE FIRST RISING EDGE AFTER
THE A/B TRANSITION WILL LATCH THE DATA.
A/B
CLK
2x
A/B
t
SI
t
SI
A
SOFT RESET
EXP[2:0]
SINGLE CHANNEL COMPLEX
IN[15:0]
A
N
CLK
A/B
N
t
LOGIC "1"
HI
t
HI
DUAL CHANNEL REAL
B
N
D
D
REGISTER
CLK
A
N+1
Q
Q
D
DELAY 7
B
N+1
CLR
ENB
B
N
×
Q
Q
A
N+2
MULTIPLEXER
S
S
1
2
B
N+2
C
D
CLK
Single Channel Complex Mode
In the Single Channel Complex input mode, A/B high identi-
fies the in-phase samples and A/B low identifies quadrature
samples. The quadrature samples are paired with the previous
in-phase samples. The timing for this mode is the same as that
of the Diversity Channel Real Mode. This mode is useful for
accepting complex output data from another AD6620 or another
source to increase filtering and or decimation rates.
In the Single Channel Complex Mode the CIC2 decimation
must be set to two (M
allow enough CLK cycles to process the complex input data as
described below.
First clock cycle: (A/B high).
– I data loaded from the input port.
– The I data-path gets I × cosine.
– The Q data-path gets I × sine.
– The first integrator of the CIC2 adds these values to its
– The rest of the CIC2 is idle.
Second clock cycle: (A/B low).
– Q data loaded from the input port.
– The I data-path gets Q × sine.
– The Q data-path gets Q × cosine.
– The first integrator of the I path of the CIC2 completes the
– The rest of the CIC2 operates on these sums, which is the
Simplified Input Data Port Schematic
Figure 27 details a simplified schematic for the input data port.
The first thing to note is that IN[15:0], EXP[2:0] and A/B are
all synchronously latched with CLK. Note also that upon soft
reset, a seven pipeline delay (sample clock delay) exists in the
data path. This delay is synchronous with CLK, but is in fact
seven valid sample data delays. For instance, in single channel
previous sums.
sum (I × cosine - Q × sine) and the first integrator of the Q
path of the CIC2 completes the sum j(I × sine + Q × cosine).
complete complex multiply. The data is then multiplexed
through the rest of the chip as if it were single channel real data.
D
D
D
REGISTER
CLR
SET
CLR
ENB
Q
Q
Q
Q
CIC2
= 2). This is necessary in order to
INT IN[15:0]
INT EXP[2:0]
INT DATA STROBE
AD6620