71M6513-IGTR/F Maxim Integrated Products, 71M6513-IGTR/F Datasheet - Page 26

• Manufacturer Part Number: 71M6513-IGTR/F
• Description: IC ENERGY METER 3PH 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of 71M6513-IGTR/F

• Mounting Style: SMD/SMT
• Package / Case: LQFP-100
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Supply Current (max): 6.4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timers and Counters
The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured for counter or timer
operations.
In timer mode, the register is incremented every machine cycle meaning that it counts up after every 12 periods of the MPU
clock signal.
In counter mode, the register is incremented when the falling edge is observed at the corresponding input signal T0 or T1 (T0
and T1 are the timer gating inputs derived from certain DIO pins, see the DIO Ports chapter). Since it takes 2 machine cycles
to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the oscillator frequency. There are no restrictions on the
duty cycle, however to ensure proper recognition of 0 or 1 state, an input should be stable for at least 1 machine cycle.
Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function Registers (TMOD and TCON) are used
to select the appropriate mode.
Timer/Counter Mode Control register (TMOD):
Bits TR1 (TCON.6) and TR0 (TCON.4) in the TCON register (see Table 21 and Table 22) start their associated timers when set.
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S1CON.7
S1CON.5
S1CON.4
S1CON.3
S1CON.2
S1CON.1
S1CON.0
A Maxim Integrated Products Brand
Bit
MSB
GATE
Symbol
SM21
REN1
TB81
RB81
RI1
SM
TI1
C/T
Timer 1
Function
Sets the baud rate for UART1
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
The 9
depending on the function it performs (parity check, multiprocessor
communication etc.)
In Modes 2 and 3, it is the 9
RB81 is the stop bit. Must be cleared by software
Transmit interrupt flag, set by hardware after completion of a serial
transfer. Must be cleared by software.
Receive interrupt flag, set by hardware after completion of a serial
reception. Must be cleared by software
M1
SM
0
1
th
© 2005-2011 Teridian Semiconductor Corporation
transmitted data bit in Mode A. Set or cleared by the MPU,
Table 17: The S1CON Bit Functions
Table 18: The TMOD Register
M0
Mode
A
B
GATE
Description
9-bit UART
8-bit UART
th
data bit received. In Mode B, if SM21 is 0,
3-Phase Energy Meter IC
C/T
Timer 0
71M6513/71M6513H
M1
Baud Rate
DATA SHEET
variable
variable
M0
LSB
AUGUST 2011