71M6521FE-IM/F Maxim Integrated Products, 71M6521FE-IM/F Datasheet - Page 77

• Manufacturer Part Number: 71M6521FE-IM/F
• Description: IC ENERGY METER 32K FLASH 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 71M6521FE-IM/F

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

71M6521DE/DH/FE Data Sheet
FLSH_ERASE[7:0]
FLSH_MEEN
FLSH_PGADR[6:0]
FLSH_PWE
FOVRIDE
IE_FWCOL0
IE_FWCOL1
IE_PB
IE_PLLRISE
IE_PLLFALL
IE_XFER
IE_RTC
IE_WAKE
INTBITS
LCD_BLKMAP19[3:0]
LCD_BLKMAP18[3:0]
LCD_CLK[1:0]
Rev 2
SFR94[7:0]
SFRB2[1]
SFRB7[7:1]
SFRB2[0]
20FD[4]
SFRE8[2]
SFRE8[3]
SFRE8[4]
SFRE8[6]
SFRE8[7]
SFRE8[0]
SFRE8[1]
SFRE8[5]
SFRF8[6:0]
205A[7:4]
205A[3:0]
2021[1:0]
--
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
--
--
--
--
--
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
This bit is automatically reset after each byte written to flash. Writes
to this bit are inhibited when interrupts are enabled.
Flash Erase Initiate
FLSH_ERASE is used to initiate either the Flash Mass Erase cycle or
the Flash Page Erase cycle. Specific patterns are expected for
FLSH_ERASE in order to initiate the appropriate Erase cycle.
(default = 0x00).
0x55 – Initiate Flash Page Erase cycle. Must be proceeded by a
0xAA – Initiate Flash Mass Erase cycle. Must be proceeded by a
Any other pattern written to FLSH_ERASE will have no effect.
Mass Erase Enable
0 – Mass Erase disabled (default).
1 – Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
Flash Page Erase Address
FLSH_PGADR[6:0] – Flash Page Address (page 0 thru 127) that will
be erased during the Page Erase cycle. (default = 0x00).
Must be re-written for each new Page Erase cycle.
Program Write Enable
0 – MOVX commands refer to XRAM Space, normal operation
1 – MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR.
Permits the values written by MPU to temporarily override the
values in the fuse register (reserved for production test).
Interrupt flags for Firmware Collision Interrupt. See Flash Memory
Section for details.
PB flag. Indicates that a rising edge occurred on PB. Firmware must
write a zero to this bit to clear it. The bit is also cleared when MPU
requests SLEEP or LCD mode. On bootup, the MPU can read this
bit to determine if the part was woken with the PB DIO0[0].
Indicates that the MPU was woken or interrupted (int 4) by System
power becoming available, or more precisely, by PLL_OK rising.
Firmware must write a zero to this bit to clear it
Indicates that the MPU has entered BROWNOUT mode because
System power has become unavailable (int 4), or more precisely,
because PLL_OK fell.
Interrupt flags. These flags monitor the XFER_BUSY interrupt and
the RTC_1SEC interrupt. The flags are set by hardware and must
be cleared by the interrupt handler. Note that IE6, the interrupt 6
flag bit in the MPU must also be cleared when either of these
interrupts occur.
Indicates that the MPU was woken by the autowake timer. This bit
is typically read by the MPU on bootup. Firmware must write a zero
to this bit to clear it
Interrupt inputs. The MPU may read these bits to see the input to
external interrupts INT0, INT1, up to INT6. These bits do not have
any memory and are primarily intended for debug use.
Identifies which segments connected to SEG18 and SEG19 should
blink. 1 means ‘blink.’ Most significant bit corresponds to COM3.
Least significant, to COM0.
Sets the LCD clock frequency (for COM/SEG pins, not frame rate).
write to FLSH_PGADR @ SFR 0xB7.
write to FLSH_MEEN @ SFR 0xB2 and the debug (CC)
port must be enabled.
Note: f
00: f
Note: this bit will not be set if the part wakes into
BROWNOUT mode because of PB or the WAKE timer.
Firmware must write a zero to this bit to clear it.
w
/2
(default).
w
9
, 01: f
= 32768Hz
w/
2
8
, 10: f
w
/2
7
, 11: f
w
/2
6
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