71M6521FE-IGT/F Maxim Integrated Products, 71M6521FE-IGT/F Datasheet - Page 21

• Manufacturer Part Number: 71M6521FE-IGT/F
• Description: IC ENERGY METER 32K FLASH 64LQFP
• Manufacturer: Maxim Integrated Products

Specifications of 71M6521FE-IGT/F

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

71M6521DE/DH/FE Data Sheet
B Register: The B register is used during multiply and divide instructions. It can also be used as a scratch-pad
register to hold temporary data.
Program Status Word (PSW):
Stack Pointer (SP): The stack pointer is a 1-byte register initialized to 0x07 after reset. This register is incremented
before PUSH and CALL instructions, causing the stack to begin at location 0x08.
Data Pointer: The data pointer (DPTR) is 2 bytes wide. The lower part is DPL, and the highest is DPH. It can be
loaded as two registers (e.g. MOV DPL,#data8). It is generally used to access external code or data space (e.g.
MOVC A,@A+DPTR or MOVX A,@DPTR respectively).
Program Counter: The program counter (PC) is 2 bytes wide initialized to 0x0000 after reset. This register is
incremented when fetching operation code or when operating on data from program memory.
Port Registers: The I/O ports are controlled by Special Function Registers P0, P1, and P2. The contents of the SFR
can be observed on corresponding pins on the chip. Writing a ‘1’ to any of the ports (see Table 11) causes the
corresponding pin to be at high level (V3P3), and writing a ‘0’ causes the corresponding pin to be held at low level
(GND). The data direction registers DIR0, DIR1, and DIR2 define individual pins as input or output pins (see section
Digital I/O for details).
Rev 2
Accumulator (ACC, A): ACC is the accumulator register. Most instructions use the accumulator to hold the
operand. The mnemonics for accumulator-specific instructions refer to accumulator as “A”, not ACC.
PSW.7
PSW.6
PSW.5
PSW.4
PSW.3
PSW.2
PSW.1
PSW.0
Bit
MSB
CV
Symbol
RS1
RS0
OV
CV
AC
F0
P
-
AC
Function
Carry flag
Auxiliary Carry flag for BCD operations
General purpose Flag 0 available for user.
Register bank select control bits. The contents of RS1 and RS0 select the working
register bank:
Overflow flag
User defined flag
Parity flag, affected by hardware to indicate odd / even number of “one” bits in the
Accumulator, i.e. even parity.
F0
F0 is not to be confused with the F0 flag in the CE STATUS register.
RS1/RS0
Table 9: PSW Register Flags
Table 10: PSW Bit Functions
00
01
10
11
RS1
Bank selected
RS
Bank 0
Bank 1
Bank 2
Bank 3
OV
-
(0x00 – 0x07)
(0x08 – 0x0F)
(0x10 – 0x17)
(0x18 – 0x1F)
Location
P
LSB
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