MAX16025TE+ Maxim Integrated Products, MAX16025TE+ Datasheet - Page 7

IC SUPERVISORY CIRC DL 16TQFN

MAX16025TE+

Manufacturer Part Number
MAX16025TE+
Description
IC SUPERVISORY CIRC DL 16TQFN
Manufacturer
Maxim Integrated Products
Type
Sequencerr
Datasheet

Specifications of MAX16025TE+

Number Of Voltages Monitored
2
Output
Open Drain or Open Collector
Reset
Active Low
Reset Timeout
140 ms/Adjustable Minimum
Voltage - Threshold
9 Selectable Threshold Combinations
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-TQFN Exposed Pad
Undervoltage Threshold
Adjustable
Overvoltage Threshold
Adjustable
Manual Reset
Resettable
Watchdog
No Watchdog
Supply Voltage (max)
28 V
Supply Voltage (min)
2.2 V
Supply Current (typ)
52 uA
Maximum Power Dissipation
2000 mW
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table
* When V
of the state of EN_ and V
in the correct state for V
MAX16025/
MAX16026
11
12
13
14
15
16
High
High
EN_
Low
Low
CC
Adjustable, Sequencing/Supervisory Circuits
1. Output State*
falls below the UVLO, all outputs go low regardless
MAX16027/
MAX16028
PIN
14
15
16
17
18
19
20
_______________________________________________________________________________________
V
V
V
V
IN_
IN_
IN_
IN_
CC
IN_
IN_
< V
< V
> V
> V
down to 1.2V.
. The outputs are guaranteed to be
Dual-/Triple-/Quad-Voltage, Capacitor-
MAX16029/
MAX16030
TH
TH
TH
TH
17
18
19
20
21
22
23
24
Low
Low
Low
OUT_ = high
(MAX16026/MAX16028/
MAX16030)
OUT_ = high impedance
(MAX16025/MAX16027/
MAX16029)
CRESET
CDLY4
CDLY3
CDLY2
CDLY1
RESET
NAME
OUT1
MR
EP
OUT_
Output 1. When the voltage at IN1 is below its threshold or EN1 goes low,
OUT1 goes low.
Active-Low Reset Output. RESET asserts low when any of the monitored
voltages (IN_) falls below its respective threshold, any EN_ goes low, or MR is
asserted. RESET remains asserted for the reset timeout period after all of the
monitored voltages exceed their respective threshold, all EN_ are high, all
OUT_ are high, and MR is deasserted.
Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET
remains low for the reset timeout period after MR is deasserted (as long as all
OUT_ are high).
Capacitor-Adjustable Reset Delay Input. Connect an external capacitor from
CRESET to GND to set the reset timeout period or connect to V
default 140ms minimum reset timeout period. Leave CRESET open for internal
propagation delay.
Capacitor-Adjustable Delay Input 4. Connect an external capacitor from
CDLY4 to GND to set the IN4 to OUT4 (and EN4 to OUT4) delay period.
Leave CDLY4 open for internal propagation delay.
Capacitor-Adjustable Delay Input 3. Connect an external capacitor from
CDLY3 to GND to set the IN3 to OUT3 (and EN3 to OUT3) delay period.
Leave CDLY3 open for internal propagation delay.
Capacitor-Adjustable Delay Input 2. Connect an external capacitor from
CDLY2 to GND to set the IN2 to OUT2 (and EN2 to OUT2) delay period.
Leave CDLY2 open for internal propagation delay.
Capacitor-Adjustable Delay Input 1. Connect an external capacitor from
CDLY1 to GND to set the IN1 to OUT1 (and EN1 to OUT1) delay period.
Leave CDLY1 open for internal propagation delay.
Exposed Pad. EP is internally connected to GND. Connect EP to the
ground plane.
Table
Low/Low
Low/High
Low/Open
High/Low
High/High
High/Open
Open/Low
Open/High
Open/Open
TH1/TH0
LOGIC
2. Input-Voltage Threshold Selector
Pin Description (continued)
VERSIONS)
IN1 (ALL
Adj
(V)
3.3
3.3
3.3
3.3
2.5
3.3
3.3
2.5
FUNCTION
VERSIONS)
IN2 (ALL
Adj
Adj
Adj
Adj
(V)
2.5
1.8
1.5
1.2
1.8
(MAX16027/
MAX16028)
IN3
(V)
1.8
Adj
Adj
1.8
Adj
2.5
Adj
Adj
Adj
CC
for the
(MAX16029/
MAX16030)
IN4
1.5
Adj
Adj
2.5
Adj
Adj
Adj
Adj
Adj
(V)
7

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