ADM690ANZ Analog Devices Inc, ADM690ANZ Datasheet - Page 8

• Manufacturer Part Number: ADM690ANZ
• Description: IC SUPERVISOR MPU 4.65 WD 8DIP
• Manufacturer: Analog Devices Inc
• Type: Battery Backup Circuitr

Specifications of ADM690ANZ

• Number Of Voltages Monitored: 1
• Output: Push-Pull, Totem Pole
• Reset: Active Low
• Reset Timeout: 35 ms Minimum
• Voltage - Threshold: 4.65V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Threshold Voltage: 4.65V
• No. Of Supervisors / Monitors: 1
• Supply Voltage Range: 1V To 5.5V
• Reset Type: Active-Low
• Supply Current: 1.95mA
• Delay Time: 200ms
• Digital Ic Case Style: DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADM690–ADM695
CE Gating and RAM Write Protection (ADM691/ADM693/
ADM695)
The ADM691/ADM693/ADM695 products include memory
protection circuitry which ensures the integrity of data in mem-
ory by preventing write operations when V
level. There are two additional pins, CE
may be used to control the Chip Enable or Write inputs of
CMOS RAM. When V
of CE
the reset voltage threshold or V
CE
CE
backed up CMOS RAM. This ensures the integrity of the data
in memory by preventing write operations when V
valid level. Similar protection of EEPROMs can be achieved by
using the CE
If the 5 ns typical propagation delay of CE
nect CE
high speed external logic gate.
LOW LINE
OUT
OUT
RESET
CE
CE
V
IN
OUT
CC
IN
high, independent of CE
typically drives the CE, CS, or write input of battery
, with a 5 ns propagation delay. When V
IN
t
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
1
= RESET TIME.
to GND and use the resulting CE
OUT
V2
CE
Figure 6. Chip Enable Timing
Figure 5. Chip Enable Gating
to drive the store or write inputs.
IN
t
1
V
V
CC
CC
CC
LOW = 0
OK = 1
is present, CE
ADM69x
V1
BATT
IN
.
, an internal gate forces
V2
IN
OUT
CC
OUT
and CE
t
1
OUT
is a buffered replica
CE
is at an invalid
is excessive, con-
OUT
CC
to control a
CC
OUT
falls below
is at an in-
, which
V1
–8–
Power Fail Warning Comparator
An additional comparator is provided for early warning of failure
in the microprocessor’s power supply. The Power Fail Input
(PFI) is compared to an internal +1.3 V reference. The Power
Fail Output (PFO) goes low when the voltage at PFI is less than
1.3 V. Typically PFI is driven by an external voltage divider
which senses either the unregulated dc input to the system’s 5 V
regulator or the regulated 5 V output. The voltage divider ratio
can be chosen such that the voltage at PFI falls below 1.3 V sev-
eral milliseconds before the +5 V power supply falls below the
reset threshold. PFO is normally used to interrupt the micropro-
cessor so that data can be stored in RAM and the shut down
procedure executed before power is lost
Signal
V
RESET
RESET
LOW LINE
BATT ON
WDI
WDO
PFI
PFO
CE
CE
OSC IN
OSC SEL
OUT
Table II. Input and Output Status In Battery Backup Mode
IN
OUT
POWER
INPUT
R
R
1
2
Figure 7. Power Fail Comparator
Status
V
PMOS switch.
Logic low.
Logic high. The open circuit output voltage is
equal to V
Logic low.
Logic high. The open circuit voltage is equal to
V
WDI is ignored. It is internally disconnected
from the internal pull-up resistor and does not
source or sink current as long as its input voltage
is between GND and V
does not affect supply current.
Logic high. The open circuit voltage is equal
to V
The Power Fail Comparator is turned off and
has no effect on the Power Fail Output.
Logic low.
CE
from its internal pull-up and does not source or
sink current as long as its input voltage is
between GND and V
does not affect supply current.
Logic high. The open circuit voltage is equal to
V
OSC IN is ignored.
OSC SEL is ignored.
OUT
OUT.
OUT
POWER
IN
INPUT
OUT
FAIL
.
is ignored. It is internally disconnected
is connected to V
.
OUT
ADM69x
.
1.3V
OUT
BATT
OUT
. The input voltage
. The input voltage
PFO
via an internal
POWER
FAIL
OUTPUT
REV. A