ADM1232ARNZ Analog Devices Inc, ADM1232ARNZ Datasheet - Page 6

• Manufacturer Part Number: ADM1232ARNZ
• Description: IC SUPERVISOR FOR CPU 8SOIC
• Manufacturer: Analog Devices Inc
• Type: Simple Reset/Power-On Resetr

Specifications of ADM1232ARNZ

• Number Of Voltages Monitored: 1
• Output: Open Drain, Push-Pull
• Reset: Active High/Active Low
• Reset Timeout: 250 ms Minimum
• Voltage - Threshold: Adjustable/Selectable
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Threshold Voltage: 4.62V
• No. Of Supervisors / Monitors: 1
• Supply Voltage Range: 4.5V To 5.5V
• Reset Type: Active-High / Active-Low
• Supply Current: 200µA
• Delay Time: 610ms
• Number Of Elements: 2
• Monitored Voltage 1 (typ): 4.5/4.75V
• Threshold Voltage 1 (max): 4.5/4.7V
• Battery Backup Switching: No
• Watchdog Timer: Yes
• Chip Enable Signals: No
• Reset Active Time: 1s
• Manual Reset: Yes
• Package Type: SOIC N
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Reset Threshold Voltage (max): 4.74/4.49V
• Reset Threshold Voltage (min): 4.5/4.25V
• Family Name: ADM1232
• Power Dissipation: 0.0009W
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Power Fail Detection: No
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADM1232
CIRCUIT INFORMATION
PB RESET
The PB RESET input makes it possible to manually reset a
system using either a standard push-button switch or a logic
low input. An internal debounce circuit provides glitch
immunity when used with a switch, reducing the effects of
glitches on the line. The debounce circuit is guaranteed to cause
the ADM1232 to assert a reset if PB RESET is brought low for
more than 20 ms and is guaranteed to ignore low inputs of less
than 1 ms.
PB RESET
RESET
RESET
Figure 6. Typical Push-Button Reset Application
PB RESET
GND
V
V
CC
CC
ADM1232
V
IL
TOLERANCE
PB RESET
DELAY
Figure 7. PB RESET
STROBE
TD
RESET
PB RESET TIME
MICROPROCESSOR
I/O
RESET
V
RESET ACTIVE
IH
TIME
Rev. C | Page 6 of 12
STROBE TIMEOUT SELECTION
TD (time delay) set is used to set the strobe timeout period. The
strobe timeout period is the maximum time between high-to-
low transitions that STROBE accepts before a reset is asserted
(see
Table 5. Strobe Timeout Settings
Condition
TD = 0 V
TD = Floating
TD = V
RESET OUTPUT DELAY
W
TOLERANCE
The TOLERANCE input is used to determine the level at which
V
Connecting TOLERANCE to GND selects a −5% tolerance level
and causes the ADM1232 to generate a reset if V
4.75 V. If TOLERANCE is connected to V
level is selected, which causes the ADM1232 to generate a reset
if V
in the Specifications section for more information.
RESET AND RESET OUTPUTS
RESET is capable of sourcing and sinking current, whereas
RESET is an open-drain MOSFET that sinks current only.
Therefore, it is necessary to pull this output high.
RESET
RESET
HEN V
CC
V
CC
can vary below 5 V without the ADM1232 asserting a reset.
CC
Figure 8
STROBE
CC
falls below 4.5 V. See the parameters for the V
CC
IS FALLING
PULSE WIDTH
). The strobe timeout settings are listed in
STROBE
5V
STROBE TIMEOUT PERIOD
Min
62.5
250
500
Figure 8. STROBE Parameters
Figure 9. Reset Output Delay
4.25V (10% TRIP POINT)
4.5V (5% TRIP POINT)
Typ
150
600
1200
Max
250
1000
2000
CC
, a −10% tolerance
RESET OUTPUT DELAY
WHEN V
5V
CC
CC
falls below
CC
IS RISING
trip point
Table 5
Unit
ms
ms
ms
.