AD8512AR Analog Devices Inc, AD8512AR Datasheet - Page 18

• Manufacturer Part Number: AD8512AR
• Description: IC OPAMP JFET 8MHZ DUAL LN 8SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD8512AR

• Slew Rate: 20 V/µs
• Mounting Type: Surface Mount
• Rohs Status: RoHS non-compliant
• Design Resources: Precision, Bipolar Configuration for the AD5546/56 DAC (CN0024) Precision, Bipolar, Configuration for AD5547/AD5557 DAC (CN0028)
• Amplifier Type: J-FET
• Number Of Circuits: 2
• Gain Bandwidth Product: 8MHz
• Current - Input Bias: 25pA
• Voltage - Input Offset: 100µV
• Current - Supply: 2.2mA
• Current - Output / Channel: 70mA
• Voltage - Supply, Single/dual (±): ±4.5 V ~ 18 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width)
• No. Of Amplifiers: 2
• Bandwidth: 20MHz
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +125°C
• Gain: 8dB
• Peak Reflow Compatible (260 C): No
• Output Type: -
• -3db Bandwidth: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD8510/AD8512/AD8513
Crosstalk
Crosstalk, also known as channel separation, is a measure of
signal feedthrough from one channel to another on the same
IC. The AD8512/AD8513 have a channel separation of better
than −90 dB for frequencies up to 10 kHz and of better than
−50 dB for frequencies up to 10 MHz. Figure 57 shows the
typical channel separation behavior between Amplifier A
(driving amplifier) and each of the following: Amplifier B,
Amplifier C, and Amplifier D.
CROSSTALK = 20 log
–100
–120
–140
–160
–20
–40
–60
–80
0
100
18V p-p
V
IN
Figure 55. Pulse-Width Modulation
2
3
Figure 56. Crosstalk Test Circuit
1k
Figure 57. Channel Separation
+V
10V
V
S
8
OUT
5kΩ
IN
TIME (2ms/DIV)
1
10k
FREQUENCY (Hz)
V
OUT
7
5kΩ
20kΩ
100k
–V
CH B
CH D
4
S
6
5
1M
CH C
2.2kΩ
10M
Rev. I | Page 18 of 20
The AD8510 single has two additional active terminals that are
not present on the AD8512 dual or AD8513 quad parts. These
pins are labeled “null” and are used for fine adjustment of the
input offset voltage. Although the guaranteed maximum offset
voltage at room temperature is 400 μV and over the −40°C to
+125°C range is 800 mV maximum, this offset voltage can be
reduced by adding a potentiometer to the null pins as shown in
Figure 58. With the 20 kΩ potentiometer shown, the adjustment
range is approximately ±3.5 mV. The potentiometer parallels
low value resistors in the drain circuit of the JFET differential
input pair and allows unbalancing of the drain currents to
change the offset voltage. If offset adjustment is not required,
these pins should be left unconnected.
Caution should be used when adding adjusting potentiometers to
any op amp with this capability for several reasons. First, there is
gain from these nodes to the output; therefore, capacitive coupling
from noisy traces to these nodes will inject noise into the signal
path. Second, the temperature coefficient of the potentiometer
will not match the temperature coefficient of the internal resistors,
so the offset voltage drift with temperature will be slightly affected.
Third, this provision is for adjusting the offset voltage of the
op amp, not for adjusting the offset of the overall system. Although
it is tempting to decrease the value of the potentiometer to attain
more range, this will adversely affect the dc and ac parameters.
Instead, increase the potentiometer to 50 kΩ to decrease the
range if needed.
INPUT
–
+
Figure 58. Optional Offset Nulling Circuit
2
3
AD8510
1
V–
5
4
20kΩ
7
V
TYPICALLY ±3.5mV
6
OS
TRIM RANGE IS
V+
OUTPUT