OP193FSZ Analog Devices Inc, OP193FSZ Datasheet - Page 14

IC OPAMP GP 35KHZ PREC 8SOIC

OP193FSZ

Manufacturer Part Number
OP193FSZ
Description
IC OPAMP GP 35KHZ PREC 8SOIC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of OP193FSZ

Slew Rate
0.015 V/µs
Design Resources
4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145)
Amplifier Type
General Purpose
Number Of Circuits
1
Output Type
Rail-to-Rail
Gain Bandwidth Product
35kHz
Current - Input Bias
20nA
Voltage - Input Offset
150µV
Current - Supply
30µA
Current - Output / Channel
25mA
Voltage - Supply, Single/dual (±)
1.7 V ~ 36 V, ±0.85 V ~ 18 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Op Amp Type
Precision
No. Of Amplifiers
1
Bandwidth
35kHz
Supply Voltage Range
2V To ± 18V
Amplifier Case Style
SOIC
No. Of Pins
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
-3db Bandwidth
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
OP193FSZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
OP193/OP293/OP493
PINS 9(LSB)–16(MSB)
5V
DAC DATA BUS
3.6k
25
24 I
23
4
5
6
I
AD589
I
I
OUT2C/2D
I
OUT2A/2B
1.23V
OUT1B
OUT1C
OUT1D
I
OUT1A
DAC8408ET
DAC8408
DAC8408
DGND
DAC8408
DAC8408
V
DAC C
DAC D
DAC A
DAC B
5V
DD
1/4
1/4
1/4
1/4
1
28
V
V
V
V
REF
REF
REF
REF
A/B
R/W
DS1
DS2
A
B
C
D
2
8
27
21
17
18
19
20
13
12
10
2
3
6
9
5
DIGITAL
CONTROL
SIGNALS
1/4 OP493
1/4 OP493
1/4 OP493
1/4 OP493
OP493
A
B
C
D
5V
4
1
11
14
7
8
R3
100k
R4
100k
R2
100k
V
V
V
V
R1
100k
OUT
OUT
OUT
OUT
B
C
D
A
A Single-Supply Micropower Quad Programmable-Gain
Amplifier
The combination of the quad OP493 and the DAC8408 quad
8-bit CMOS DAC creates a quad programmable-gain amplifier
with a quiescent supply drain of only 140 µA (Figure 14). The
digital code present at the DAC, which is easily set by a micro-
processor, determines the ratio between the fixed DAC feedback
resistor and the resistance that the DAC feedback ladder pre-
sents to the op amp feedback loop. The gain of each amplifier is:
where n equals the decimal equivalent of the 8-bit digital code
present at the DAC.
If the digital code present at the DAC consists of all zeros, the
feedback loop will be open causing the op amp to saturate. The
10 MΩ resistors placed in parallel with the DAC feedback loop
eliminates this problem with a very small reduction in gain
accuracy. The 2.5 V reference biases the amplifiers to the center
of the linear region providing maximum output swing.
V
V
OUT
IN
=
256
n

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