C8051F312 Silicon Laboratories Inc, C8051F312 Datasheet - Page 70

• Manufacturer Part Number: C8051F312
• Description: IC 8051 MCU 8K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F31xr

Specifications of C8051F312

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 29
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 21x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 336-1151

C8051F310/1/2/3/4/5/6/7
The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis-
abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state,
and its supply current falls to less than 100 nA. See
page 131
externally driven from –0.25 V to (V
trical specifications are given in Table 7.1.
The Comparator response time may be configured in software via the CPTnMD registers (see SFR Defini-
tion 7.3 and SFR Definition 7.6). Selecting a longer response time reduces the Comparator supply current.
See Table 7.1 for complete timing and current consumption specifications.
70
CMX1N1
CMX1N0
CMX1P1
CMX1P0
for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be
P1.2
P1.6
P2.2
P2.6
P1.3
P1.7
P2.3
P2.7
Figure 7.2. Comparator1 Functional Block Diagram
CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0
CP1OUT
CP1RIF
CP1FIF
CP1EN
DD
) + 0.25 V without damage or upset. The complete Comparator elec-
CP1 +
CP1 -
CP1MD1
CP1MD0
CP1RIE
CP1FIE
Rev. 1.7
+
-
GND
VDD
Section “13.1. Priority Crossbar Decoder” on
Decision
Reset
Tree
(SYNCHRONIZER)
D
SET
CLR
Q
Q
D
SET
CLR
Q
Q
Rising-edge
CP1
Crossbar
Interrupt
Logic
Falling-edge
Interrupt
CP1
CP1A
CP1
CP1