C8051F301 Silicon Laboratories Inc, C8051F301 Datasheet
C8051F301
Specifications of C8051F301
Available stocks
Related parts for C8051F301
C8051F301 Summary of contents
Page 1
ANALOG PERIPHERALS - 8-Bit ADC • 500 ksps • External Inputs • Programmable Amplifier Gains & 0.5 • VREF from External Pin or VDD • Built-in Temperature Sensor • External Conversion ...
Page 2
C8051F300/1/2/3/4/5 2 Notes Rev. 2.3 ...
Page 3
TABLE OF CONTENTS 1. SYSTEM OVERVIEW .........................................................................................................11 1.1. CIP-51™ Microcontroller Core ......................................................................................14 1.1.1. Fully 8051 Compatible ..........................................................................................14 1.1.2. Improved Throughput ............................................................................................14 1.1.3. Additional Features................................................................................................15 1.2. On-Chip Memory ............................................................................................................16 1.3. On-Chip Debug Circuitry ................................................................................................17 1.4. Programmable Digital I/O and Crossbar .........................................................................18 ...
Page 4
C8051F300/1/2/3/4/5 8.3.4. Interrupt Latency....................................................................................................68 8.3.5. Interrupt Register Descriptions ..............................................................................70 8.4. Power Management Modes .............................................................................................75 8.4.1. Idle Mode ...............................................................................................................75 8.4.2. Stop Mode..............................................................................................................75 9. RESET SOURCES ................................................................................................................77 9.1. Power-On Reset...............................................................................................................78 9.2. Power-Fail Reset / VDD Monitor....................................................................................78 9.3. External Reset..................................................................................................................79 9.4. Missing Clock ...
Page 5
Master Transmitter Mode ....................................................................................115 13.5.2. Master Receiver Mode.........................................................................................116 13.5.3. Slave Receiver Mode ...........................................................................................117 13.5.4. Slave Transmitter Mode.......................................................................................118 13.6. SMBus Status Decoding................................................................................................119 14. UART0 ..................................................................................................................................123 14.1. Enhanced Baud Rate Generation...................................................................................124 14.2.Operational Modes ........................................................................................................125 14.2.1. 8-Bit UART .........................................................................................................125 14.2.2. 9-Bit UART ...
Page 6
C8051F300/1/2/3/4/5 6 Notes Rev. 2.3 ...
Page 7
... SYSTEM OVERVIEW Table 1.1. Product Selection Guide ......................................................................................12 Figure 1.1. C8051F300/2 Block Diagram..............................................................................12 Figure 1.2. C8051F301/3/4/5 Block Diagram .......................................................................13 Figure 1.3. Comparison of Peak MCU Execution Speeds.....................................................14 Figure 1.4. On-Chip Clock and Reset....................................................................................15 Figure 1.5. On-chip Memory Map (C8051F300/1/2/3 shown)..............................................16 Figure 1.6. Development/In-System Debug Diagram ...........................................................17 Figure 1 ...
Page 8
C8051F300/1/2/3/4/5 7. COMPARATOR0 Figure 7.1. Comparator0 Functional Block Diagram ............................................................47 Figure 7.2. Comparator Hysteresis Plot.................................................................................48 Figure 7.3. CPT0CN: Comparator0 Control Register ...........................................................49 Figure 7.4. CPT0MX: Comparator0 MUX Selection Register..............................................50 Figure 7.5. CPT0MD: Comparator0 Mode Selection Register..............................................51 Table 7.1. Comparator0 Electrical ...
Page 9
Figure 11.4. OSCXCN: External Oscillator Control Register.................................................92 12. PORT INPUT/OUTPUT Figure 12.1. Port I/O Functional Block Diagram ....................................................................95 Figure 12.2. Port I/O Cell Block Diagram...............................................................................95 Figure 12.3. Crossbar Priority Decoder with XBR0 = 0x00 ...................................................96 Figure 12.4. Crossbar Priority Decoder ...
Page 10
C8051F300/1/2/3/4/5 Figure 15.1. T0 Mode 0 Block Diagram................................................................................134 Figure 15.2. T0 Mode 2 Block Diagram................................................................................135 Figure 15.3. T0 Mode 3 Block Diagram................................................................................136 Figure 15.4. TCON: Timer Control Register.........................................................................137 Figure 15.5. TMOD: Timer Mode Register...........................................................................138 Figure 15.6. CKCON: Clock Control Register......................................................................139 ...
Page 11
SYSTEM OVERVIEW C8051F300/1/2/3/4/5 devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 1.1 on page 12 for specific product feature selection. • High-speed pipelined 8051-compatible microcontroller core ( MIPS) • In-system, ...
Page 12
... C8051F300/1/2/3/4/5 Table 1.1. Product Selection Guide C8051F300 25 8k 256 C8051F301 25 8k 256 C8051F302 25 8k 256 C8051F303 25 8k 256 C8051F304 25 4k 256 C8051F305 25 2k 256 Figure 1.1. C8051F300/2 Block Diagram Analog/Digital VDD Power GND C2D Debug HW /RST/C2CK Brown- POR Out External XTAL1 ...
Page 13
... Figure 1.2. C8051F301/3/4/5 Block Diagram Analog/Digital VDD Power GND C2D Debug HW Reset /RST/C2CK Brown- POR Out External XTAL1 Oscillator XTAL2 Circuit System Clock Precision Internal Oscillator C8051F300/1/2/3/4/5 Port I/O Mode & Config. 8 Port 0 Latch 0 8k/4k/2k byte x2 UART 5 FLASH 1 Timer 0, 1 256 byte ...
Page 14
C8051F300/1/2/3/4/5 1.1. CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F300/1/2/3/4/5 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. ...
Page 15
Additional Features The C8051F300/1/2/3/4/5 SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. The extended interrupt handler provides 12 interrupt sources into the CIP-51 (as opposed ...
Page 16
C8051F300/1/2/3/4/5 1.2. On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and ...
Page 17
On-Chip Debug Circuitry The C8051F300/1/2/3/4/5 devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides non-intru- sive, full speed, in-circuit debugging of the production part installed in the end application. Silicon Labs' debugging system supports inspection and modification ...
Page 18
C8051F300/1/2/3/4/5 1.4. Programmable Digital I/O and Crossbar C8051F300/1/2/3/4/5 devices include a byte-wide I/O Port that behaves like a typical 8051 Port with a few enhance- ments. Each Port pin may be configured as an analog input or a digital I/O ...
Page 19
Programmable Counter Array An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the three 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with three programmable cap- ture/compare modules. The PCA clock ...
Page 20
C8051F300/1/2/3/4/5 1.7. 8-Bit Analog to Digital Converter (C8051F300/2 Only) The C8051F300/2 includes an on-chip 8-bit SAR ADC with a 10-channel differential input multiplexer and program- mable gain amplifier. With a maximum throughput of 500 ksps, the ADC offers true 8-bit ...
Page 21
Comparator C8051F300/1/2/3/4/5 devices include an on-chip voltage comparator that is enabled/disabled and configured via user software. All Port I/O pins may be configurated as comparator inputs. Two comparator outputs may be routed to a Port pin if desired: a ...
Page 22
C8051F300/1/2/3/4/5 2. ABSOLUTE MAXIMUM RATINGS Table 2.1. Absolute Maximum Ratings PARAMETER Ambient temperature under bias Storage Temperature Voltage on any Port I/O Pin or /RST with respect to GND Voltage on VDD with respect to GND Maximum Total current through ...
Page 23
GLOBAL DC ELECTRICAL CHARACTERISTICS Table 3.1. Global DC Electrical Characteristics -40°C to +85°C, 25 MHz System Clock unless otherwise specified. PARAMETER Digital Supply Voltage Digital Supply Current with VDD=2.7V, Clock=25MHz CPU active VDD=2.7V, Clock=1MHz VDD=2.7V, Clock=32kHz Digital Supply Current ...
Page 24
C8051F300/1/2/3/4/5 4. PINOUT AND PACKAGE DEFINITIONS Table 4.1. Pin Definitions for the C8051F300/1/2/3/4/5 Pin Number Name 1 VREF / P0.0 2 P0.1 3 VDD 4 XTAL1 / P0.2 5 XTAL2 / P0.3 6 P0.4 7 P0.5 8 C2CK / /RST ...
Page 25
Figure 4.1. MLP-11 Pinout Diagram (Top View) VREF / P0.0 P0.1 VDD XTAL1 / P0.2 XTAL2 / P0.3 C8051F300/1/2/3/4/5 CNVSTR GND Rev. 2.3 C2D / P0.7 P0.6 / C2CK / /RST P0.5 P0.4 25 ...
Page 26
C8051F300/1/2/3/4/5 Figure 4.2. MLP-11 Package Drawing Bottom View Side E View e Side D View e 26 Table 4.2. MLP-11 Package Diminsions E3 MIN A 0. 0.18 D ...
Page 27
Figure 4.3. Typical MLP-11 Solder Mask 0.10 mm 0.35 mm 0.50 mm 0. C8051F300/1/2/3/4 0.50 mm 0.35 mm 0. 0.60 mm 0. Rev. 2.3 ...
Page 28
C8051F300/1/2/3/4/5 Figure 4.4. Typical MLP-11 Landing Diagram 0.10 mm 0.35 mm 0.50 mm 0. 0. Rev. 2.3 ...
Page 29
C8051F300/1/2/3/4/5 Notes Rev. 2.3 29 ...
Page 30
C8051F300/1/2/3/4/5 30 Rev. 2.3 ...
Page 31
ADC0 (8-BIT ADC, C8051F300/2) The ADC0 subsystem for the C8051F300/2 consists of two analog multiplexers (referred to collectively as AMUX0) with 11 total input selections, a differential programmable gain amplifier (PGA), and a 500 ksps, 8-bit successive- approximation-register ADC ...
Page 32
C8051F300/1/2/3/4/5 5.1. Analog Multiplexer and PGA The analog multiplexers (AMUX0) select the positive and negative inputs to the PGA, allowing any Port pin to be measured relative to any other Port pin or GND. Additionally, the on-chip temperature sensor or ...
Page 33
Temperature Sensor The typical temperature sensor transfer function is shown in Figure 5.2. The output voltage (V PGA input when the temperature sensor is selected by bits AMX0P2-0 in register AMX0SL; this voltage will be amplified by the PGA ...
Page 34
C8051F300/1/2/3/4/5 Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V) 5.00 4.00 3.00 2.00 1.00 0.00 -40.00 -20.00 -1.00 -2.00 -3.00 -4.00 -5.00 34 40.00 0.00 20.00 Temperature (degrees C) Rev. 2.3 5.00 4.00 3.00 2.00 1.00 ...
Page 35
Modes of Operation ADC0 has a maximum conversion speed of 500 ksps. The ADC0 conversion clock is a divided version of the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by (AD0SC + ...
Page 36
C8051F300/1/2/3/4/5 5.3.2. Tracking Modes The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is continuously tracked except when a conversion is in progress. When the AD0TM bit is logic 1, ADC0 ...
Page 37
Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different AMUX0 or PGA selection is made), a minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the ...
Page 38
C8051F300/1/2/3/4/5 Figure 5.6. AMX0SL: AMUX0 Channel Select Register (C8051F300/2) R/W R/W R/W AMX0N3 AMX0N2 AMX0N1 AMX0N0 AMX0P3 Bit7 Bit6 Bit5 Bits7-4: AMX0N3-0: AMUX0 Negative Input Selection. Note that when GND is selected as the Negative Input, ADC0 operates in Single-ended ...
Page 39
Figure 5.7. ADC0CF: ADC0 Configuration Register (C8051F300/2) R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 Bit7 Bit6 Bit5 Bits7-3: AD0SC4-0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to ...
Page 40
C8051F300/1/2/3/4/5 Figure 5.9. ADC0CN: ADC0 Control Register (C8051F300/2) R/W R/W R/W AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 Bit7 Bit6 Bit5 Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ...
Page 41
Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output to user-programmed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU ...
Page 42
C8051F300/1/2/3/4/5 5.4.2. Window Detector In Differential Mode Figure 5.11 shows two example window comparisons for differential mode, with ADC0LT = 0x10 (+16d) and ADC0GT = 0xFF (-1d). Notice that in Differential mode, the codes vary from -VREF to VREF*(127/128) and ...
Page 43
Figure 5.12. ADC0GT: ADC0 Greater-Than Data Byte Register (C8051F300/2) R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: ADC0 Greater-Than Data Word. Figure 5.13. ADC0LT: ADC0 Less-Than Data Byte Register (C8051F300/2) R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: ADC0 Less-Than Data Word. ...
Page 44
C8051F300/1/2/3/4/5 Table 5.1. ADC0 Electrical Characteristics VDD = 3.0 V, VREF = 2.40 V (REFSL=0), PGA Gain = 1, -40°C to +85°C unless otherwise specified PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Offset Temperature ...
Page 45
VOLTAGE REFERENCE (C8051F300/2) The voltage reference MUX on C8051F300/2 devices is configurable to use an externally connected voltage refer- ence or the power supply voltage, VDD (see Figure 6.1). The REFSL bit in the Reference Control register (REF0CN) selects ...
Page 46
C8051F300/1/2/3/4/5 Figure 6.2. REF0CN: Reference Control Register R/W R/W R Bit7 Bit6 Bit5 Bits7-3: UNUSED. Read = 00000b; Write = don’t care. Bit3: REFSL: Voltage Reference Select. This bit selects the source for the internal voltage reference. ...
Page 47
COMPARATOR0 C8051F300/1/2/3/4/5 devices include an on-chip programmable voltage comparator, which is shown in Figure 7.1. Comparator0 offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous ...
Page 48
C8051F300/1/2/3/4/5 The output of Comparator0 can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, the Comparator0 output is available asynchronous or synchronous to the system clock; the ...
Page 49
Comparator0 interrupts can be generated on both rising-edge and falling-edge output transitions. (For Interrupt enable and priority control, see Section “8.3. Interrupt Handler” on page upon a Comparator0 falling-edge interrupt, and the CP0RIF flag is set to logic 1 upon ...
Page 50
C8051F300/1/2/3/4/5 Figure 7.4. CPT0MX: Comparator0 MUX Selection Register R/W R/W R CMX0N1 CMX0N0 Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 00b, Write = don’t care. Bits6-4: CMX0N1-CMX0N0: Comparator0 Negative Input MUX Select. These bits select which Port pin ...
Page 51
Figure 7.5. CPT0MD: Comparator0 Mode Selection Register R/W R/W R Bit7 Bit6 Bit5 Bits7-2: UNUSED. Read = 000000b, Write = don’t care. Bits1-0: CP0MD1-CP0MD0: Comparator0 Mode Select. These bits select the response time for Comparator0. Mode CP0MD1 ...
Page 52
C8051F300/1/2/3/4/5 Table 7.1. Comparator0 Electrical Characteristics VDD = 3.0 V, -40°C to +85°C unless otherwise specified. PARAMETER CP0+ - CP0- = 100 mV Response Time: † Mode 0, Vcm = 1.5 V CP0+ - CP0- = -100 mV CP0+ - ...
Page 53
CIP-51 MICROCONTROLLER The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of ...
Page 54
C8051F300/1/2/3/4/5 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture standard 8051, all instructions except for MUL and DIV take system clock cycles to exe- cute, ...
Page 55
INSTRUCTION SET The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the binary and ...
Page 56
C8051F300/1/2/3/4/5 Table 8.1. CIP-51 Instruction Set Summary Mnemonic Description MUL AB Multiply A and B DIV AB Divide Decimal adjust A ANL A, Rn AND Register to A ANL A, direct AND direct byte to ...
Page 57
Table 8.1. CIP-51 Instruction Set Summary Mnemonic Description MOV DPTR, #data16 Load DPTR with 16-bit constant MOVC A, @A+DPTR Move code byte relative DPTR to A MOVC A, @A+PC Move code byte relative MOVX A, @Ri Move ...
Page 58
C8051F300/1/2/3/4/5 Table 8.1. CIP-51 Instruction Set Summary Mnemonic Description CJNE @Ri, #data, rel Compare immediate to indirect and jump if not equal DJNZ Rn, rel Decrement Register and jump if not zero DJNZ direct, rel Decrement direct byte and jump ...
Page 59
MEMORY ORGANIZATION The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two sepa- rate memory spaces: program memory and data memory. Program and data memory share the same address space ...
Page 60
C8051F300/1/2/3/4/5 8.2.2. Data Memory The CIP-51 includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either ...
Page 61
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where XX is the byte address and B is the bit position within the byte. For example, the instruction: MOV C, 22.3h moves the Boolean ...
Page 62
C8051F300/1/2/3/4/5 Table 8.2. Special Function Register (SFR) Memory Map F8 CPT0CN PCA0L PCA0H F0 B P0MDIN E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 E0 ACC XBR0 XBR1 D8 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 D0 PSW REF0CN C8 TMR2CN TMR2RLL TMR2RLH C0 ...
Page 63
Table 8.3. Special Function Registers Register Address Description FLKEY 0xB7 FLASH Lock and Key FLSCL 0xB6 FLASH Scale IE 0xA8 Interrupt Enable IP 0xB8 Interrupt Priority IT01CF 0xE4 INT0/INT1 Configuration Register OSCICL 0xB3 Internal Oscillator Calibration OSCICN 0xB2 Internal Oscillator ...
Page 64
C8051F300/1/2/3/4/5 Table 8.3. Special Function Registers Register Address Description XBR0 0xE1 Port I/O Crossbar Control 0 XBR1 0xE2 Port I/O Crossbar Control 1 XBR2 0xE3 Port I/O Crossbar Control 2 0x97, 0xAE, 0xAF, 0xB4, 0xB6, 0xBF, 0xCE, 0xD2, 0xD3, 0xD4, ...
Page 65
Figure 8.6. SP: Stack Pointer R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: SP: Stack Pointer. The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented before every PUSH operation. The SP register defaults ...
Page 66
C8051F300/1/2/3/4/5 R/W R/W R/W ACC.7 ACC.6 ACC.5 Bit7 Bit6 Bit5 Bits7-0: ACC: Accumulator. This register is the accumulator for arithmetic operations. R/W R/W R/W B.7 B.6 B.5 Bit7 Bit6 Bit5 Bits7- Register. This register serves as a second ...
Page 67
Interrupt Handler The CIP-51 includes an extended interrupt system supporting a total of 12 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the spe- cific version ...
Page 68
C8051F300/1/2/3/4/5 8.3.2. External Interrupts The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or active ...
Page 69
Table 8.4. Interrupt Summary Interrupt Interrupt Source Vector Reset 0x0000 External Interrupt 0 (/INT0) 0x0003 Timer 0 Overflow 0x000B External Interrupt 1 (/INT1) 0x0013 Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SMBus Interface 0x0033 ADC0 Window Compare ...
Page 70
C8051F300/1/2/3/4/5 8.3.5. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the ...
Page 71
Figure 8.11. IP: Interrupt Priority R/W R/W R PT2 Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 11b, Write = don't care. Bit5: PT2: Timer 2 Interrupt Priority Control. This bit sets the priority of the Timer 2 interrupt. ...
Page 72
C8051F300/1/2/3/4/5 Figure 8.12. EIE1: Extended Interrupt Enable 1 R/W R/W R ECP0R Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 00b. Write = don’t care. Bit5: ECP0R: Enable Comparator0 (CP0) Rising Edge Interrupt. This bit sets the masking of ...
Page 73
Figure 8.13. EIP1: Extended Interrupt Priority 1 R/W R/W R PCP0R Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 11b. Write = don’t care. Bit5: PCP0R: Comparator0 (CP0) Rising Interrupt Priority Control. This bit sets the priority of the ...
Page 74
C8051F300/1/2/3/4/5 Figure 8.14. IT01CF: INT0/INT1 Configuration Register R/W R/W R/W IN1PL IN1SL2 IN1SL1 Bit7 Bit6 Bit5 Note: Refer to Figure 15.4 for INT0/1 edge- or level-sensitive interrupt selection. Bit7: IN1PL: /INT1 Polarity 0: /INT1 input is active low. 1: /INT1 ...
Page 75
Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all interrupts and timers ...
Page 76
C8051F300/1/2/3/4/5 Figure 8.15. PCON: Power Control Register R/W R/W R/W GF5 GF4 GF3 Bit7 Bit6 Bit5 Bits7-2: GF5-GF0: General Purpose Flags 5-0. These are general purpose flags for use under software control. Bit1: STOP: Stop Mode Select. Setting this bit ...
Page 77
RESET SOURCES Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • CIP-51 halts program execution • Special Function Registers (SFRs) are initialized to their ...
Page 78
C8051F300/1/2/3/4/5 9.1. Power-On Reset During power-up, the device is held in a reset state and the /RST pin is driven low until VDD settles above V delay occurs before the device is released from reset; the delay decreases as the ...
Page 79
Important Note: Enabling the VDD monitor will immediately generate a system reset. The device will then return from the reset state with the VDD monitor enabled. Writing a logic ‘1’ to the PORSF flag when the VDD monitor is enabled ...
Page 80
C8051F300/1/2/3/4/5 Table 9.1. User Code Space Address Limits Device C8051F305 The FERROR bit (RSTSRC.6) is set following a FLASH error reset. The state of the /RST pin is unaffected by this reset. 9.8. Software Reset Software may force a reset ...
Page 81
Figure 9.3. RSTSRC: Reset Source Register R R R/W - FERROR C0RSEF Bit7 Bit6 Bit5 (Note: Do not use read-modify-write operations (ORL, ANL) on this register) Bit7: UNUSED. Read = 0. Write = don’t care. Bit6: FERROR: FLASH Error Indicator. ...
Page 82
C8051F300/1/2/3/4/5 82 Notes Rev. 2.3 ...
Page 83
FLASH MEMORY On-chip, re-programmable FLASH memory is included for program code and non-volatile data storage. The FLASH memory can be programmed in-system, a single byte at a time, through the C2 interface or by software using the MOVX instruction. ...
Page 84
C8051F300/1/2/3/4/5 10.1.3. FLASH Write Procedure FLASH bytes are programmed by software with the following sequence: Step 1. Disable interrupts (recommended). Step 2. Erase the 512-byte FLASH page containing the target location, as described in Step 3. Set the PSWE bit ...
Page 85
Non-volatile Data Storage The FLASH memory can be used for non-volatile data storage as well as program code. This allows data such as cal- ibration coefficients to be calculated and stored at run time. Data is written using the ...
Page 86
C8051F300/1/2/3/4/5 Figure 10.2. PSCTL: Program Store R/W Control R/W R/W R Bit7 Bit6 Bit5 Bits7-2: UNUSED: Read = 000000b, Write = don’t care. Bit1: PSEE: Program Store Erase Enable Setting this bit (in combination with PSWE) allows ...
Page 87
Figure 10.3. FLKEY: FLASH Lock and Key Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: FLKEY: FLASH Lock and Key Register Write: This register must be written to before FLASH writes or erases can be performed. FLASH remains locked until ...
Page 88
C8051F300/1/2/3/4/5 88 Notes Rev. 2.3 ...
Page 89
OSCILLATORS C8051F300/1/2/3/4/5 devices include a programmable internal oscillator and an external oscillator drive circuit. The internal oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure 11.1. The system clock can be sourced ...
Page 90
C8051F300/1/2/3/4/5 Figure 11.2. OSCICL: Internal Oscillator Calibration Register R/W R/W R/W - Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 0. Write = don’t care. Bits 6-0: OSCICL: Internal Oscillator Calibration Register. This register calibrates the internal oscillator period. The reset ...
Page 91
Table 11.1. Internal Oscillator Electrical Characteristics -40°C to +85°C unless otherwise specified PARAMETER Calibrated Internal Oscillator Frequency Uncalibrated Internal Oscillator Frequency Internal Oscillator Supply Current (from VDD) 11.2. External Oscillator Drive Circuit The external oscillator circuit may drive an external ...
Page 92
C8051F300/1/2/3/4/5 Figure 11.4. OSCXCN: External Oscillator Control Register R R/W R/W XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Bit7 Bit6 Bit5 Bit7: XTLVLD: Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable. 1: ...
Page 93
External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 11.1, Option 1. The External Oscillator Frequency Control value (XFCN) should ...
Page 94
C8051F300/1/2/3/4/5 94 Notes Rev. 2.3 ...
Page 95
PORT INPUT/OUTPUT Digital and analog resources are available through a byte-wide digital I/O Port, Port0. Each of the Port pins can be defined as general-purpose I/O (GPIO), analog input, or assigned to one of the internal digital resources as ...
Page 96
C8051F300/1/2/3/4/5 12.1. Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 12.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource ...
Page 97
Figure 12.4. Crossbar Priority Decoder with XBR0 = 0x44 SF Signals VREF PIN I TX0 RX0 SDA SCL CP0 CP0A SYSCLK CEX0 CEX1 CEX2 ECI Port pin potentially available to peripheral Port pin skipped ...
Page 98
C8051F300/1/2/3/4/5 12.2. Port I/O Initialization Port I/O initialization consists of the following steps: Step 1. Select the input mode (analog or digital) for all Port pins, using the Port0 Input Mode register (P0MDIN). Step 2. Select the output mode (open-drain ...
Page 99
Figure 12.5. XBR0: Port I/O Crossbar Register 0 R/W R/W R/W - XSKP6 XSKP5 Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 0b; Write = don’t care. Bits6-0: XSKP[6:0]: Crossbar Skip Enable Bits These bits select Port pins to be skipped ...
Page 100
C8051F300/1/2/3/4/5 Figure 12.7. XBR2: Port I/O Crossbar Register 2 R/W R/W R/W WEAKPUD XBARE - Bit7 Bit6 Bit5 Bit7: WEAKPUD: Port I/O Weak Pull-up Disable. 0: Weak Pull-ups enabled (except for Ports whose I/O are configured as push-pull). 1: Weak ...
Page 101
General Purpose Port I/O Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for general pur- pose I/O. Port0 is accessed through a corresponding special function register (SFR) that is ...
Page 102
C8051F300/1/2/3/4/5 Figure 12.10. P0MDOUT: Port0 Output Mode Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: Output Configuration Bits for P0.7-P0.0 (respectively): ignored if corresponding bit in register P0MDIN is logic 0. 0: Corresponding P0.n Output is open-drain. 1: Corresponding P0.n ...
Page 103
SMBUS The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Manage- ment Bus Specification, version 1.1, and compatible with the I system controller are byte oriented with the SMBus interface autonomously ...
Page 104
C8051F300/1/2/3/4/5 13.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents The I C-Bus and How to Use It (including specifications), Philips Semiconductor The I C-Bus Specification ...
Page 105
SMBus Operation Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ). The master device ini- tiates ...
Page 106
C8051F300/1/2/3/4/5 13.3.2. Clock Low Extension SMBus provides a clock synchronization mechanism, similar to I bilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. ...
Page 107
Using the SMBus The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting control for serial transfers; higher level protocol is determined by user software. The SMBus interface provides the following applica- tion-independent ...
Page 108
C8051F300/1/2/3/4/5 13.4.1. SMBus Configuration Register The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the ...
Page 109
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high. The minimum SDA hold time defines ...
Page 110
C8051F300/1/2/3/4/5 Figure 13.5. SMB0CF: SMBus Clock/Configuration Register R/W R/W R ENSMB INH BUSY Bit7 Bit6 Bit5 Bit7: ENSMB: SMBus Enable. This bit enables/disables the SMBus interface. When enabled, the interface constantly monitors the SDA and SCL pins. 0: SMBus interface ...
Page 111
SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see Figure 13.6). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to jump ...
Page 112
C8051F300/1/2/3/4/5 Figure 13.6. SMB0CN: SMBus Control Register R R R/W MASTER TXMODE STA Bit7 Bit6 Bit5 Bit7: MASTER: SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. 0: SMBus operating in Slave Mode. 1: ...
Page 113
Table 13.3. Sources for Hardware Changes to SMB0CN Bit Set by Hardware When: • A START is generated. MASTER • START is generated. • The SMBus interface enters transmitter mode TXMODE (after SMB0DAT is written before the start of an ...
Page 114
C8051F300/1/2/3/4/5 13.4.3. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is ...
Page 115
SMBus Transfer Modes The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver. ...
Page 116
C8051F300/1/2/3/4/5 13.5.2. Master Receiver Mode Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the ...
Page 117
Slave Receiver Mode Serial data is received on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the inter- face enters Slave Receiver Mode when a START followed by a slave address ...
Page 118
C8051F300/1/2/3/4/5 13.5.4. Slave Transmitter Mode Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START ...
Page 119
SMBus Status Decoding The current SMBus status can be easily decoded using the SMB0CN register. In the table below, STATUS VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. Note that the shown response ...
Page 120
C8051F300/1/2/3/4/5 Table 13.4. SMBus Status Decoding VALUES READ CURRENT SMBUS STATE A slave byte was transmitted; NACK received. A slave byte was transmitted; ACK 0100 received. A Slave byte was transmitted; error 0 1 ...
Page 121
Table 13.4. SMBus Status Decoding VALUES READ CURRENT SMBUS STATE A slave address was received; ACK requested. 0010 Lost arbitration as master; slave address received; ACK requested. Lost arbitration while attempting a 0010 0 ...
Page 122
C8051F300/1/2/3/4/5 122 Notes Rev. 2.3 ...
Page 123
UART0 UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in “14.1. Enhanced ...
Page 124
C8051F300/1/2/3/4/5 14.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer ...
Page 125
Operational Modes UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown below. Figure 14.3. UART Interconnect Diagram 14.2.1. 8-Bit UART 8-Bit UART ...
Page 126
C8051F300/1/2/3/4/5 14.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit. The state of the ninth transmit data ...
Page 127
Multiprocessor Communications 9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave pro- cessors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, ...
Page 128
C8051F300/1/2/3/4/5 Figure 14.7. SCON0: Serial Port 0 Control Register R/W R/W R/W S0MODE - MCE0 Bit7 Bit6 Bit5 Bit7: S0MODE: Serial Port 0 Operation Mode. This bit selects the UART0 Operation Mode. 0: Mode 0: 8-bit UART with Variable Baud ...
Page 129
Figure 14.8. SBUF0: Serial (UART0) Port Data Buffer Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: SBUF0[7:0]: Serial Data Buffer Bits 7-0 (MSB-LSB) This SFR accesses two registers; a transmit shift register and a receive latch register. When data is ...
Page 130
C8051F300/1/2/3/4/5 Table 14.1. Timer Settings for Standard Baud Rates Using The Internal Oscillator Target Baud Rate Baud Rate % Error (bps) 230400 -0.32% 115200 -0.32% 57600 0.15% 28800 -0.32% 14400 0.15% 9600 -0.32% 2400 -0.32% 1200 0.15 Don’t ...
Page 131
Table 14.3. Timer Settings for Standard Baud Rates Using an External Oscillator Target Baud Rate Oscillator Baud Rate % Error Divide (bps) Factor 230400 0.00% 115200 0.00% 57600 0.00% 28800 0.00% 14400 0.00% 9600 0.00% 2400 0.00% 1200 0.00% 230400 ...
Page 132
C8051F300/1/2/3/4/5 Table 14.5. Timer Settings for Standard Baud Rates Using an External Oscillator Target Baud Rate Baud Rate % Error (bps) 230400 0.00% 115200 0.00% 57600 0.00% 28800 0.00% 14400 0.00% 9600 0.00% 2400 0.00% 1200 0.00% 230400 0.00% 115200 ...
Page 133
TIMERS Each MCU includes 3 counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and one is a 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose use. These timers can ...
Page 134
C8051F300/1/2/3/4/5 Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal /INT0 is active as defined by bit IN0PL in register INT01CF (see Figure 8.14). Setting GATE0 to ‘1’ allows the ...
Page 135
Mode 2: 8-bit Counter/Timer with Auto-Reload Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. TL0 holds the count and TH0 holds the reload value. When the counter ...
Page 136
C8051F300/1/2/3/4/5 15.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/timer in TL0 is controlled using the Timer 0 control/status bits in ...
Page 137
Figure 15.4. TCON: Timer Control Register R/W R/W R/W TF1 TR1 TF0 Bit7 Bit6 Bit5 Bit7: TF1: Timer 1 Overflow Flag. Set by hardware when Timer 1 overflows. This flag can be cleared by software but is automatically cleared when ...
Page 138
C8051F300/1/2/3/4/5 Figure 15.5. TMOD: Timer Mode Register R/W R/W R/W GATE1 C/T1 T1M1 Bit7 Bit6 Bit5 Bit7: GATE1: Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level. 1: Timer 1 enabled only ...
Page 139
Figure 15.6. CKCON: Clock Control Register R/W R/W R/W - T2MH T2ML Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 0b, Write = don’t care. Bit6: T2MH: Timer 2 High Byte Clock Select This bit selects the clock supplied to the ...
Page 140
C8051F300/1/2/3/4/5 Figure 15.7. TL0: Timer 0 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: TL0: Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0 Figure 15.8. TL1: Timer 1 Low Byte ...
Page 141
Timer 2 Timer 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may oper- ate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines ...
Page 142
C8051F300/1/2/3/4/5 15.2.2. 8-bit Timers with Auto-Reload When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers operate in auto- reload mode as shown in Figure 15.12. TMR2RLL holds the reload value for TMR2L; ...
Page 143
Figure 15.13. TMR2CN: Timer 2 Control Register R/W R/W R/W TF2H TF2L TF2LEN Bit7 Bit6 Bit5 Bit7: TF2H: Timer 2 High Byte Overflow Flag Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00 ...
Page 144
C8051F300/1/2/3/4/5 Figure 15.14. TMR2RLL: Timer 2 Reload Register Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: TMR2RLL: Timer 2 Reload Register Low Byte. TMR2RLL holds the low byte of the reload value for Timer 2. Figure 15.15. TMR2RLH: ...
Page 145
PROGRAMMABLE COUNTER ARRAY The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU interven- tion than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and three 16-bit capture/compare modules. Each capture/compare module ...
Page 146
C8051F300/1/2/3/4/5 16.1. PCA Counter/Timer The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of ...
Page 147
Capture/Compare Modules Each module can be configured to operate independently in one of six operation modes: Edge-triggered Capture, Software Timer, High Speed Output, Frequency Output, 8-Bit Pulse Width Modulator, or 16-Bit Pulse Width Modu- lator. Each module has Special ...
Page 148
C8051F300/1/2/3/4/5 16.2.1. Edge-triggered Capture Mode In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/timer and copy it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). The ...
Page 149
Software Timer (Compare) Mode In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and ...
Page 150
C8051F300/1/2/3/4/5 16.2.3. High Speed Output Mode In High Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn) Setting the TOGn, MATn, ...
Page 151
Frequency Output Mode Frequency Output Mode produces a programmable-frequency square wave on the module’s associated CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the output is toggled. The frequency of the ...
Page 152
C8051F300/1/2/3/4/5 16.2.5. 8-Bit Pulse Width Modulator Mode Each module can be used independently to generate a pulse width modulated (PWM) output on its associated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer. ...
Page 153
Using Equation 16.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is 0.39% (PCA0CPHn = 0xFF duty cycle may be generated by clearing the ECOMn bit to ‘0’. Figure 16.8. PCA 8-Bit ...
Page 154
C8051F300/1/2/3/4/5 16.2.6. 16-Bit Pulse Width Modulator Mode A PCA module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare module defines the number of PCA clocks for the low time of the PWM signal. When ...
Page 155
C8051F300/1/2/3/4/5 Rev. 2.3 155 ...
Page 156
C8051F300/1/2/3/4/5 16.3. Watchdog Timer Mode A programmable watchdog timer (WDT) function is available through the PCA Module 2. The WDT is used to gen- erate a reset if the time between writes to the WDT update register (PCA0CPH2) exceed a ...
Page 157
Note that the 8-bit offset held in PCA0CPH2 is compared to the upper byte of the 16-bit PCA counter. This offset value is the number of PCA0L overflows before a reset 256 PCA clocks may pass before the ...
Page 158
C8051F300/1/2/3/4/5 16.4. Register Descriptions for PCA Following are detailed descriptions of the special function registers related to the operation of the PCA. Figure 16.11. PCA0CN: PCA Control Register R/W R/W R Bit7 Bit6 Bit5 Bit7: CF: PCA ...
Page 159
Figure 16.12. PCA0MD: PCA Mode Register R/W R/W R/W CIDL WDTE WDLCK Bit7 Bit6 Bit5 Bit7: CIDL: PCA Counter/Timer Idle Control. Specifies PCA behavior when CPU is in Idle Mode. 0: PCA continues to function normally while the system controller ...
Page 160
C8051F300/1/2/3/4/5 Figure 16.13. PCA0CPMn: PCA Capture/Compare Mode Registers R/W R/W R/W PWM16n ECOMn CAPPn Bit7 Bit6 Bit5 PCA0CPMn Address: PCA0CPM0 = 0xDA ( PCA0CPM1 = 0xDB ( PCA0CPM2 = 0xDC ( Bit7: PWM16n: 16-bit ...
Page 161
Figure 16.14. PCA0L: PCA Counter/Timer Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: PCA0L: PCA Counter/Timer Low Byte. The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer. Figure 16.15. PCA0H: PCA Counter/Timer High Byte ...
Page 162
C8051F300/1/2/3/4/5 Figure 16.16. PCA0CPLn: PCA Capture Module Low Byte R/W R/W R/W Bit7 Bit6 Bit5 PCA0CPLn Address: PCA0CPL0 = 0xFB ( PCA0CPL1 = 0xE9 ( PCA0CPL2 = 0xEB ( Bits7-0: PCA0CPLn: PCA Capture Module ...
Page 163
C2 INTERFACE C8051F300/1/2/3/4/5 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow FLASH pro- gramming, boundary scan functions, and in-system debugging with the production part installed in the end applica- tion. The C2 interface operates similar ...
Page 164
C8051F300/1/2/3/4/5 Figure 17.3. REVID: C2 Revision ID Register Bit7 Bit6 Bit5 This read-only register returns the 8-bit revision ID: 0x00 (Revision A) Figure 17.4. FPCTL: C2 FLASH Programming Control Register Bit7 Bit6 Bit5 Bits7-0 FPCTL: FLASH Programming Control Register This ...
Page 165
C2 Pin Sharing The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging, FLASH program- ming, and boundary scan functions may be performed. This is possible because C2 communication is typically per- ...
Page 166
... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unautho- rized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. ...