MC68332ACPV25 Freescale Semiconductor, MC68332ACPV25 Datasheet - Page 74

• Manufacturer Part Number: MC68332ACPV25
• Description: IC MCU 32-BIT 25MHZ A MASK
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332ACPV25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: Q1501580

SPCR1 — QSPI Control Register 1
SPE — QSPI Enable
DSCKL — Delay before SCK
DTL — Length of Delay after Transfer
74
MOTOROLA
RESET:
SPE
15
0
SCK baud rate:
where SPBR equals {2, 3, 4,..., 255}
Giving SPBR a value of zero or one disables the baud rate generator. SCK is disabled and assumes its
inactive state value. No serial transfers occur. At reset, baud rate is initialized to one eighth of the sys-
tem clock frequency.
SPCR1 contains parameters for configuring the QSPI before it is enabled. The CPU can read and write
this register, but the QSM has read access only, except for SPE, which is automatically cleared by the
QSPI after completing all serial transfers, or when a mode fault occurs.
When the DSCK bit in command RAM is set, this field determines the length of delay from PCS valid to
SCK transition. PCS can be any of the four peripheral chip-select pins. The following equation deter-
mines the actual delay before SCK:
where DSCKL equals {1, 2, 3,..., 127}.
When the DSCK value of a queue entry equals zero, then DSCKL is not used. Instead, the PCS valid-
to-SCK transition is one-half SCK period.
When the DT bit in command RAM is set, this field determines the length of delay after serial transfer.
The following equation is used to calculate the delay:
where DTL equals {1, 2, 3,..., 255}.
A zero value for DTL causes a delay-after-transfer value of 8192/System Clock.
If DT equals zero, a standard delay is inserted.
Delay after transfer can be used to provide a peripheral deselect interval. A delay can also be inserted
between consecutive transfers to allow serial A/D converters to complete conversion.
0 = QSPI is disabled. QSPI pins can be used for general-purpose I/O.
1 = QSPI is enabled. Pins allocated by PQSPAR are controlled by the QSPI.
14
0
0
0
Freescale Semiconductor, Inc.
DSCKL
SPBR = System Clock/(2SCK)(Baud Rate Desired)
Standard Delay after Transfer = [17/System Clock]
For More Information On This Product,
0
Delay after Transfer = [(32DTL)/System Clock]
PCS to SCK Delay = [DSCKL/System Clock]
SCK Baud Rate = System Clock/(2SPBR)
1
Go to: www.freescale.com
0
8
0
or
7
0
0
0
0
DTL
0
1
MC68332TS/D
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0
MC68332
0
0