MC68HC11F1CFN4 Freescale Semiconductor, MC68HC11F1CFN4 Datasheet - Page 82

• Manufacturer Part Number: MC68HC11F1CFN4
• Description: IC MCU 512 EEPROM 4MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11F1CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 30
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -

DDRA — Data Direction Register for Port A
DDA[7:0] — Data Direction for Port A
6.2 Port B
PORTB — Port B Data
6.3 Port C
6-2
S. Chip or
Expan. or
RESET:
Boot:
RESET:
Test:
Reset state is mode dependent. In single-chip or bootstrap modes, port B pins are
general-purpose outputs. In expanded and test modes, port B pins are high-order ad-
dress outputs and PORTB is not in the memory map.
Reset state is mode dependent. In single-chip and bootstrap modes, port C pins are
high-impedance inputs. It is customary to have an external pull-up resistor on lines that
are driven by open-drain devices. In expanded or test modes, port C pins are data bus
inputs/outputs and PORTC is not in the memory map. The R/W signal is used to con-
trol the direction of data transfers.
The CWOM control bit in the OPT2 register disables port C's P-channel output drivers.
Because the N-channel driver is not affected by CWOM, setting CWOM causes port
C to become an open-drain-type output port suitable for wired-OR operation. In wired-
OR mode, (PORTC bits are at logic level zero), pins are actively driven low by the N-
channel driver. When a port C bit is at logic level one, the associated pin is in a high-
0 = Input
1 = Output
ADDR15
DDA7
Bit 7
Bit 7
PB7
PB7
0
0
To enable PA3 as fourth input capture, set the I4/O5 bit in the PACTL
register. Otherwise, PA3 is configured as a fifth output compare out
of reset, with bit I4/O5 being cleared. If the DDA3 bit is set (configur-
ing PA3 as an output), and IC4 is enabled, writes to PA3 cause edges
on the pin to result in input captures. Writing to TI4/O5 has no effect
when the TI4/O5 register is acting as IC4. PA7 drives the pulse ac-
cumulator input but also can be configured for general-purpose I/O,
or output compare. Note that even when PA7 is configured as an out-
put, the pin still drives the pulse accumulator input.
ADDR14
DDA6
PB6
PB6
6
0
6
0
Freescale Semiconductor, Inc.
For More Information On This Product,
ADDR13
DDA5
PB5
PB5
5
0
5
0
PARALLEL INPUT/OUTPUT
Go to: www.freescale.com
ADDR12
DDA4
PB4
PB4
4
0
4
0
NOTE
ADDR11
DDA3
PB3
PB3
0
3
0
3
ADDR10
DDA2
PB2
PB2
2
0
2
0
ADDR9
DDA1
PB1
PB1
1
0
1
0
ADDR8
TECHNICAL DATA
DDA0
Bit 0
Bit 0
PB0
PB0
0
0
MC68HC11F1
$1001
$1004