PIC18C252-E/SP Microchip Technology, PIC18C252-E/SP Datasheet - Page 3

• Manufacturer Part Number: PIC18C252-E/SP
• Description: IC MCU OTP 16KX16 A/D 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C252-E/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18C252E/SP

7. Module: MSSP (I
 2002 Microchip Technology Inc.
The BF Status bit (SSPSTAT<0>) may be inadvert-
ently cleared, even if the buffer has not been read.
This will occur when both of the following two
conditions are met:
•
•
Work around
All work arounds involve setting the BSR to some
value other than 0Fh. Other solutions may exist in
addition to the work arounds proposed below.
1. When developing or modifying code, keep
2. If accessing a part of Bank 15 is required and
3. If pointing the BSR to Bank 15 is unavoidable,
The four Least Significant bits of the BSR
are equal to 0Fh (BSR<3:0> = '1111'), and
Any instruction that contains C9h in its 8
Least Significant bits (i.e., register file
address, literal data, instruction address
offset, etc.) is executed.
these guidelines in mind:
•
•
•
the use of Access Banking is not possible,
consider using indirect addressing.
review the absolute file listing. Verify that no
instruction contains C9h in the 8 Least
Significant bits while BSR points to Bank 15
(BSR = 0Fh).
Assign 12-bit addresses to all variables.
This allows the assembler to know when
Access Banking can be used.
Do not set the BSR to point to Bank 15
(BSR = 0Fh).
Allow the assembler to manipulate the
Access bit present in most instructions.
Accessing SFRs in Bank 15 will be done
through the Access Bank. Continue to
use the BSR to select Banks 1 through 5
and the upper half of Bank 0.
2
C Master Mode)
8. Module: Interrupts
9. Module: Watchdog Timer
10. Module: WDT
High priority interrupts may become improperly
enabled, while low priority interrupts become
improperly disabled at the same time. This may
occur when low priority interrupts are in an
enabled state and the following conditions occur
simultaneously:
•
•
Work around
Always disable low priority interrupts before dis-
abling high priority interrupts. Re-enable the low
priority interrupts afterward, if necessary.
After the WDT is allowed to time-out, all subse-
quent WDT periods following the very first, may
double in duration. This can occur if the CLRWDT
instruction is not executed prior to the timer timing
out.
Work around
Always execute the CLRWDT instruction prior to
entering a potential WDT time-out condition.
When the device is configured for either EC or RC
oscillator modes, with the Power-up Timer
enabled, bit TO of the RCON register (RCON<3>)
may default to ‘0’, even though no WDT time-out
has occurred.
The TO bit functions normally in all other configu-
rations.
Work around
1. Use bit TO in conjunction with bit POR
High priority interrupts are being changed
from an enabled to a disabled state
One or more low priority interrupts occur
(RCON<1>), to determine if a RESET condi-
tion has occurred.
PIC18CXX2
DS80058H-page 3