ATMEGA163L-4PI Atmel, ATMEGA163L-4PI Datasheet - Page 108

• Manufacturer Part Number: ATMEGA163L-4PI
• Description: IC AVR MCU 16K A/D 2.7V 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA163L-4PI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

108
ATmega163(L)
When initiating a conversion by setting the ADSC bit in ADCSR, the conversion starts at
the following rising edge of the ADC clock cycle.
A normal conversion takes 13 ADC clock cycles. In certain situations, the ADC needs
more clock cycles to initalization and minimize offset errors. Extended conversions take
25 ADC clock cycles and occur as the first conversion after the ADC is switched on
(ADEN in ADCSR is set). Additionally, when changing voltage reference, the user may
improve accuracy by disregarding the first conversion result after the reference or MUX
setting was changed.
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal
conversion and 13.5 ADC clock cycles after the start of an extended conversion. When
a conversion is complete, the result is written to the ADC Data Registers, and ADIF is
set. In Single Conversion mode, ADSC is cleared simultaneously. The software may
then set ADSC again, and a new conversion will be initated on the first rising ADC clock
edge. In Free Running mode, a new conversion will be started immediately after the
conversion completes, while ADSC remains high. Using Free Running mode and an
ADC clock frequency of 200 kHz gives the lowest conversion time with a maximum res-
olution, 65 s, equivalent to 15 kSPS. For a summary of conversion times, see Table
39.
Figure 59. ADC Timing Diagram, Extended Conversion (Single Conversion Mode)
Figure 60. ADC Timing Diagram, Single Conversion
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
ADC Clock
ADEN
ADSC
ADIF
ADCH
ADCL
1
1
2
MUX and REFS
update
2
MUX and REFS
Update
12
3
13
Sample & Hold
4
14
5
15
6
Sample & Hold
16
Extended Conversion
17
7
One Conversion
18
8
19
9
20
10
Conversion
Complete
21
11
22
Conversion
Complete
23
12
24
13
25
Sign and MSB of Result
LSB of Result
Sign and MSB of Result
LSB of Result
Next Conversion
1
1142E–AVR–02/03
Next
Conversion
1
2
MUX and REFS
Update
2
MUX and REFS
Update
3
3