AT90LS8535-4AC Atmel, AT90LS8535-4AC Datasheet - Page 73

• Manufacturer Part Number: AT90LS8535-4AC
• Description: IC MCU 8K 4MHZ A/D LV 44TQFP
• Manufacturer: Atmel
• Series: AVR® 90LSr

Specifications of AT90LS8535-4AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADC Data Register – ADCL
AND ADCH
1041H–11/01
ADSC will read as one as long as a conversion is in progress. When the conversion is
complete, it returns to zero. When a extended conversion precedes a real conversion,
ADSC will stay high until the real conversion completes. Writing a “0” to this bit has no
effect.
• Bit 5 – ADFR: ADC Free Running Select
When this bit is set (one), the ADC operates in Free Running Mode. In this mode, the
ADC samples and updates the data registers continuously. Clearing this bit (zero) will
terminate Free Running Mode.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set (one) when an ADC conversion completes and the data registers are
updated. The ADC Conversion Complete interrupt is executed if the ADIE bit and the I-
bit in SREG are set (one). ADIF is cleared by hardware when executing the correspond-
ing interrupt handling vector. Alternatively, ADIF is cleared by writing a logical “1” to the
flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be dis-
abled. This also applies if the SBI and CBI instructions are used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Com-
plete interrupt is activated.
• Bits 2..0 – ADPS2..ADPS0: ADC Prescaler Select Bits
These bits determine the division factor between the XTAL frequency and the input
clock to the ADC.
Table 28. ADC Prescaler Selections
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Conse-
quently, it is essential that both registers are read and that ADCL is read before ADCH.
Bit
$05 ($25)
$04 ($24)
Read/Write
Initial Value
ADPS2
0
0
0
0
1
1
1
1
ADC7
15
R
R
–
7
0
0
ADC6
ADPS1
14
R
R
–
6
0
0
0
0
1
1
0
0
1
1
ADC5
13
R
R
–
5
0
0
ADC4
12
R
R
–
4
0
0
ADPS0
0
1
0
1
0
1
0
1
ADC3
11
R
R
–
3
0
0
ADC2
10
R
R
–
2
0
0
AT90S/LS8535
ADC9
ADC1
Division Factor
R
R
9
1
0
0
128
16
32
64
2
2
4
8
ADC8
ADC0
R
R
8
0
0
0
ADCH
ADCL
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