AT91R40807-33AI Atmel, AT91R40807-33AI Datasheet - Page 75
AT91R40807-33AI
Manufacturer Part Number
AT91R40807-33AI
Description
IC ARM7 MCU 176 TQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT91R40807-33AC.pdf
(19 pages)
2.AT91R40807-33AC.pdf
(20 pages)
3.AT91R40807-33AI.pdf
(153 pages)
Specifications of AT91R40807-33AI
Core Processor
ARM7
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, UART/USART
Peripherals
WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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Interrupts
User Interface
1354D–ATARM–08/02
Each parallel I/O can be programmed to generate an interrupt when a level change
occurs. This is controlled by the PIO_IER (Interrupt Enable) and PIO_IDR (Interrupt Dis-
able) registers which enable/disable the I/O interrupt by setting/clearing the
corresponding bit in the PIO_IMR. When a change in level occurs, the corresponding bit
in the PIO_ISR (Interrupt Status) is set whether the pin is used as a PIO or a peripheral
and whether it is defined as input or output. If the corresponding interrupt in PIO_IMR
(Interrupt Mask) is enabled, the PIO interrupt is asserted.
When PIO_ISR is read, the register is automatically cleared.
Each individual I/O is associated with a bit position in the Parallel I/O user interface reg-
isters. Each of these registers are 32 bits wide. If a parallel I/O line is not defined, writing
to the corresponding bits has no effect. Undefined bits read zero.
AT91X40 Series
75
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