PIC17LC756-08/SP Microchip Technology, PIC17LC756-08/SP Datasheet - Page 151

• Manufacturer Part Number: PIC17LC756-08/SP
• Description: MICRO CTRL 16K LOW PWR 64SDIP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17LC756-08/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Other names: PIC17LC756-08/P

15.2.5
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET, or when the MSSP module is
disabled. Control of the I
P bit is set, or the bus is idle, with both the S and P bits
clear.
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
FIGURE 15-17:
2000 Microchip Technology Inc.
SDA
SCL
MASTER MODE
SSP BLOCK DIAGRAM (I
2
C bus may be taken when the
SDA In
Bus Collision
SCL In
Read
Write Collision Detect
MSb
START bit, STOP bit,
START bit Detect,
end of XMIT/RCV
State Counter for
Clock Arbitration
STOP bit Detect
Acknowledge
SSPBUF
Generate
SSPSR
2
C MASTER MODE)
LSb
Write
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
Clock
Data Bus
Shift
Internal
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
PIC17C7XX
SSPADD<6:0>
SSPM3:SSPM0
Baud
Rate
Generator
DS30289B-page 151