PIC16C74/JW Microchip Technology, PIC16C74/JW Datasheet - Page 73

• Manufacturer Part Number: PIC16C74/JW
• Description: MICRO CTRL 4K 20MHZ EPROM 40CDIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C74/JW

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: EPROM, UV
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-CDIP (0.600", 15.24mm) Window
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

10.1.4
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in capture mode,
the prescaler counter is cleared. This means that any
reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore the first capture may be from
a non-zero prescaler. Example 10-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 10-1: CHANGING BETWEEN
CLRF
MOVLW
MOVWF
10.2
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven High
• Driven Low
• Remains Unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
FIGURE 10-3: COMPARE MODE
RC2/CCP1
Pin
1997 Microchip Technology Inc.
Special event trigger will:
Output Enable
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>)
which starts an A/D conversion (CCP1 only for PIC16C72,
CCP2 only for PIC16C73/73A/74/74A/76/77).
TRISC<2>
CCP1CON
NEW_CAPT_PS
CCP1CON
CCP PRESCALER
Compare Mode
Applicable Devices
72 73 73A 74 74A 76 77
Q
Special Event Trigger
OPERATION BLOCK
DIAGRAM
R
S
CCP1CON<3:0>
Mode Select
CAPTURE PRESCALERS
Output
Logic
;Turn CCP module off
;Load the W reg with
; the new prescaler
; mode value and CCP ON
;Load CCP1CON with this
; value
(PIR1<2>)
Set flag bit CCP1IF
match
CCPR1H CCPR1L
TMR1H
Comparator
TMR1L
10.2.1
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
10.2.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
10.2.3
When generate software interrupt is chosen the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
10.2.4
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The special trigger output of CCP2 resets the TMR1
register pair, and starts an A/D conversion (if the A/D
module is enabled).
For the PIC16C72 only, the special event trigger output
of CCP1 resets the TMR1 register pair, and starts an
A/D conversion (if the A/D module is enabled).
Note:
Note:
CCP PIN CONFIGURATION
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
The
CCP1and CCP2 modules will not set inter-
rupt flag bit TMR1IF (PIR1<0>).
special
event
PIC16C7X
trigger
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