DS5001FP-16 Maxim Integrated Products, DS5001FP-16 Datasheet - Page 5

• Manufacturer Part Number: DS5001FP-16
• Description: IC MPU 128K 16MHZ 80-TQFP
• Manufacturer: Maxim Integrated Products
• Series: DS500xr

Specifications of DS5001FP-16

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SIO, UART/USART
• Peripherals: Power-Fail Reset, WDT
• Number Of I /o: 32
• Program Memory Type: SRAM
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-MQFP, 80-PQFP
• Processor Series: DS5001FP
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Size: 128 KB
• Data Ram Size: 128 KB
• Interface Type: UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

PIN DESCRIPTION (continued)
4, 6, 20,
80 PIN
53, 16,
80, 76,
24, 26,
28, 30,
33, 35,
71, 69,
67, 65,
61, 59,
57, 55
8, 18,
37
10
74
72
63
62
78
22
23
32
2
3
PIN
44 PIN
41, 36,
42, 32,
30, 34,
35, 43,
1, 2, 3,
4, 5, 7,
28, 26,
24, 23,
21, 20,
19, 18
37
29
—
33
22
—
—
—
—
—
—
9
NAME
BA14–
BD7–0
PROG
R/
CE1N
BA0
CE1
CE2
CE3
CE4
PE1
PE2
PE3
PE4
W
Byte-Wide Address Bus Bits 14–0. This bus is combined with the nonmultiplexed
data bus (BD7–0) to access NV SRAM. Decoding is performed using
R/
used, BA13 and BA14 are unconnected. If a 128k SRAM is used, the micro converts
Byte-Wide Data Bus Bits 7–0. This 8-bit, bidirectional bus is combined with the
nonmultiplexed address bus (BA14–0) to access NV SRAM. Decoding is performed
on
an SRAM, and optionally to a real-time clock or other peripheral.
Read/Write. This signal provides the write enable to the SRAMs on the byte-wide
bus. It is controlled by the memory map and partition. The blocks selected as
program (ROM) are write-protected.
Chip Enable 1. This is the primary decoded chip enable for memory access on the
byte-wide bus. It connects to the chip enable input of one SRAM.
backed. It remains in a logic high inactive state when V
Non-Battery-Backed Version of Chip Enable 1. This can be used with a 32kB
EPROM. It should not be used with a battery-backed chip.
Chip Enable 2. This chip enable is provided to access a second 32k block of
memory. It connects to the chip enable input of one SRAM. When MSEL = 0, the
micro converts
remains at a logic high when V
Chip Enable 3. This chip enable is provided to access a third 32k block of memory.
It connects to the chip enable input of one SRAM. When MSEL = 0, the micro
converts
a logic high when V
Chip Enable 4. This chip enable is provided to access a fourth 32k block of
memory. It connects to the chip-enable input of one SRAM. When MSEL = 0, this
signal is unused.
Peripheral Enable 1. Accesses data memory between addresses 0000h and 3FFFh
when the PES bit is set to a logic 1. Commonly used to chip enable a byte-wide real-
time clock such as the DS1283.
when V
Peripheral Enable 2. Accesses data memory between addresses 4000h and 7FFFh
when the PES bit is set to a logic 1.
high when V
Peripheral Enable 3. Accesses data memory between addresses 8000h and BFFFh
when the PES bit is set to a logic 1.
to any type of peripheral function. If connected to a battery-backed chip, it needs
additional circuitry to maintain the chip enable in an inactive state when V
Peripheral Enable 4. Accesses data memory between addresses C000h and FFFFh
when the PES bit is set to a logic 1.
to any type of peripheral function. If connected to a battery-backed chip, it needs
additional circuitry to maintain the chip enable in an inactive state when V
Invokes the bootstrap loader on a falling edge. This signal should be debounced
so that only one edge is detected. If connected to ground, the micro enters bootstrap
loading on power-up. This signal is pulled up internally.
CE4
CE2
W
CE1
. Therefore, BA15 is not actually needed. Read/write access is controlled by
and
. BA14–0 connect directly to an 8k, 32k, or 128k SRAM. If an 8k RAM is
and
CC
CE3
CE3
falls below V
CE2
CC
to serve as A16 and A15 respectively.
into A15 for a 128k x 8 SRAM.
falls below V
CE2
. Read/write access is controlled by R/
CE4
CC
into A16 for a 128k x 8 SRAM.
5 of 27
is lithium-backed and remains at a logic high when V
falls below V
LI
. Connect
LI
. Connect
CC
PE1
falls below V
FUNCTION
PE1
PE2
PE3
PE4
LI
is lithium-backed and remains at a logic high
.
to battery-backed functions only.
is lithium-backed and remains at a logic
is not lithium-backed and can be connected
is not lithium-backed and can be connected
PE2
to battery-backed functions only.
CE3
LI
.
is lithium-backed and remains at
CE2
W
CC
. BD7–0 connect directly to
is lithium-backed and
falls below V
CE1
CE1
is lithium-
LI
.
CC
CC
through
DS5001FP
CC
< V
< V
< V
LI
LI
LI
.
.
.