SAF-C164CI-LM CA+ Infineon Technologies, SAF-C164CI-LM CA+ Datasheet - Page 63

• Manufacturer Part Number: SAF-C164CI-LM CA+
• Description: IC MCU 16BIT FLASH 80-MQFP
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C164CI-LM CA+

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SPI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-SQFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: ASC, CAN, SSC
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Packages: PG-MQFP-80
• Max Clock Frequency: 20.0 MHz
• Sram (incl. Cache): 4.0 KByte
• Can Nodes: 1
• A / D Input Lines (incl. Fadc): 8
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SP000017582

Multiplexed Bus (cont’d)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2
Parameter
RD, WR low time
(no RW-delay)
RD to valid data in
(with RW-delay)
RD to valid data in
(no RW-delay)
ALE low to valid data in
Address to valid data in
Data hold after RD
rising edge
Data float after RD
Data valid to WR
Data hold after WR
ALE rising edge after RD,
WR
Address hold after RD,
WR
ALE falling edge to CS
CS low to Valid Data In
CS hold after RD, WR
ALE fall. edge to RdCS,
WrCS (with RW delay)
Data Sheet
1)
1)
1)
t
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
A
13
14
15
16
17
18
19
22
23
25
27
38
39
40
42
+
t
CC 50 +
CC 20 +
CC 26 +
CC 26 +
CC 26 +
CC -4 -
CC 46 +
CC 16 +
SR –
SR –
SR –
SR –
SR 0
SR –
SR –
C
+
t
F
min.
Max. CPU Clock
(120 ns at 25 MHz CPU clock without waitstates)
t
= 25 MHz
A
t
t
t
t
t
t
t
59
C
C
F
F
F
F
A
max.
–
20 +
40 +
40 +
+
50 + 2
+
–
26 +
–
–
–
–
10 -
40
+
+ 2
–
–
t
t
t
C
C
C
t
A
t
t
t
t
t
A
C
C
A
F
t
A
1 / 2TCL = 1 to 25 MHz
min.
3TCL - 10
+
–
–
–
–
0
–
2TCL - 20
+
2TCL - 14
+
2TCL - 14
+
2TCL - 14
+
-4 -
–
3TCL - 14
+
TCL - 4
+
Variable CPU Clock
t
t
t
t
t
t
t
C
C
F
F
F
F
A
t
A
max.
–
2TCL - 20
+
3TCL - 20
+
3TCL - 20
+
4TCL - 30
+ 2
–
2TCL - 14
+
–
–
–
–
10 -
3TCL - 20
+
–
–
t
t
t
t
t
C
C
A
F
C
t
A
C164CL/SL
+
t
+ 2
V2.0, 2001-05
A
+
C164CI/SI
t
C
t
t
C
A
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns