SAF-XE164G-24F66L AC Infineon Technologies, SAF-XE164G-24F66L AC Datasheet - Page 46

• Manufacturer Part Number: SAF-XE164G-24F66L AC
• Description: IC MCU 16BIT FLASH 100-LQFP
• Manufacturer: Infineon Technologies
• Series: XE16xr

Specifications of SAF-XE164G-24F66L AC

• Core Processor: C166SV2
• Core Size: 16-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
• Peripherals: I²S, POR, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 192KB (192K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: SP000363795

XE164x
XE166 Family Derivatives
Functional Description
3.5
On-Chip Debug Support (OCDS)
The On-Chip Debug Support system built into the XE164 provides a broad range of
debug and emulation features. User software running on the XE164 can be debugged
within the target system environment.
The OCDS is controlled by an external debugging device via the debug interface. This
consists of the JTAG port conforming to IEEE-1149. The debug interface can be
completed with an optional break interface.
The debugger controls the OCDS with a set of dedicated registers accessible via the
debug interface (JTAG). In addition the OCDS system can be controlled by the CPU, e.g.
by a monitor program. An injection interface allows the execution of OCDS-generated
instructions by the CPU.
Multiple breakpoints can be triggered by on-chip hardware, by software, or by an
external trigger input. Single stepping is supported, as is the injection of arbitrary
instructions and read/write access to the complete internal address space. A breakpoint
trigger can be answered with a CPU halt, a monitor call, a data transfer, or/and the
activation of an external signal.
Tracing data can be obtained via the debug interface, or via the external bus interface
for increased performance.
The JTAG interface uses four interface signals, to communicate with external circuitry.
The debug interface can be amended with two optional break lines.
Data Sheet
44
V2.1, 2008-08