M30281F6HP#U5B Renesas Electronics America, M30281F6HP#U5B Datasheet - Page 105

• Manufacturer Part Number: M30281F6HP#U5B
• Description: IC M16C/28 MCU FLASH 48K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30281F6HP#U5B

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M
R
R
9.7 NMI Interrupt
9.8 Key Input Interrupt
e
E
1
. v
Figure 9.12 Key Input Interrupt
J
6
0
_______
_______
An NMI interrupt request is generated when input on the NMI pin changes state from high to low, after the
NMI interrupt was enabled by writing a “1” to bit 4 of register PM2. The NMI interrupt is a non-maskable
interrupt, once it is enabled.
The input level of this NMI interrupt input pin can be read by accessing the P8 register’s P8_5 bit.
NMI is disabled by default after reset (the pin is a GPIO pin, P8
register. Once enabled, it can only be disabled by a reset signal.
The NMI input has an effective digital debounce function for a noise rejection. Refer to "17.6 Digital
Debounce function" for this detail. When using NMI interrupt to exit stop mode, set the NDDR register to
"FF
A key input interrupt is generated when input on any of the P10
PD10_7 bits in the PD10 register set to “0” (input) goes low. Key input interrupts can be used as a key-on
wakeup function, the function to exit wait or stop mode. However, if you intend to use the key input interrupt,
do not use P10
interrupt. Note, however, that while input on any pin which has had the PD10_4 to PD10_7 bits set to “0”
(input mode) is pulled low, inputs on all other pins of the port are not detected as interrupts.
C
2
9
2 /
0 .
B
______
_______
0
16
0
8
0
_______
" before entering stop mode.
G
4
Pull-up
transistor
J
7
a
o r
0 -
. n
u
KI
KI
KI
KI
2
3
p
0
2
3
1
0
, 1
0
(
M
2
Pull-up
transistor
0
1
Pull-up
transistor
4
Pull-up
transistor
0
6
7
to P10
C
2 /
, 8
_______
page 83
M
7
1
as analog input ports. Figure 9.12 shows the block diagram of the key input
6
PD10_4 bit in the
PD10 register
PD10_5 bit in the
PD10 register
PD10_6 bit in the
PD10 register
C
PD10_7 bit in the PD10 register
2 /
f o
8
3
) B
8
5
PU25 bit in the PUR2
register
PD10_7 bit in the
PD10 register
_______
_______
4
to P10
5
Interrupt control circuit
) and can be enabled using bit 4 of PM2
KUPIC register
7
pins which has had the PD10_4 to
______
Key input interrupt
request
9. Interrupts