M30262F6GP#U3 Renesas Electronics America, M30262F6GP#U3 Datasheet

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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...

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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

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M16C FAMILY / M16C/20 SERIES 16 M16C/26 Group Hardware Manual RENESAS 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to ...

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Keep safety first in your circuit designs! Renesas Technology Corporation puts the maximum effort into making semiconductor prod- • ucts better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may ...

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This hardware manual provides detailed information on features in the M16C/26 Group microcomputer. Users are expected to have basic knowledge of electric circuits, logical circuits and micro- computer. Each register diagram contains bit functions with the following symbols and descriptions. ...

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M16C Family Documents Document Short Sheet Data Sheet Hardware Manual Software Manual Application Note Contents Hardware overview Hardware overview and electrical characteristics Hardware specifications (pin assignments, memory maps, specifications of peripheral func- tions, electrical characteristics, timing charts) Detailed description about ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Table of Contents Table of Contents Description .......................................................................................................................................... 1 Functional Block Operation ............................................................................................................... 8 Memory .......................................................................................................................................... 8 Central Processing Unit (CPU) ..................................................................................................... 9 Reset .................................................................................................................................................. 12 ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Description Description Features 2 Note bus is a registered trademark of Koninklijke Philips Electronics N. V. Note 2: IEBus is a registered trademark ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Description Applications Pin Configuration P10 /AN / P10 /AN / P10 /AN / P10 ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Description Block Diagram 3 I/O Ports Port P1 Internal Peripheral Functions Timer Timer A0 (16 bits) Timer A1 (16 bits) Timer A2 (16 bits) Timer A3 ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Description Performance Outline Table 1.1. Performance outline Parameters Number of Basic Instructions Shortest Instruction Execution Time Flash ROM (Note 3) Memory Flash ROM as Virtual EEPROM ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Description M16C Family Group Type No. M30 Figure 1.3. M3026x Product Family Table 1.2a. Product list Type No. Package Type M30262F3GP ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Description Table 1.2c. Product Marking (top view) 0262F8 A D3 XXXXX 6 Product Name => indicates M30262F8 Chip Version and Product Code: A => indicates chip ...

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...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Pin Description Pin Description Pin name Signal name Power supply input CNV CNV SS SS RESET Reset input IV Power supply ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Memory 00000 16 SFR area 00400 16 Internal RAM area XXXXX 16 RESERVED 0F000 Virtual EEPROM 16 0F800 Virtual EEPROM 16 10000 16 RESERVED YYYYY 16 ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. CPU Central Processing Unit (CPU) The CPU has a total of 13 registers shown in Figure 1.4.2. Seven of these registers (R0, R1, R2, R3, A0, ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. CPU (3) Frame base register (FB) Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing. (4) Program counter (PC) ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. CPU • Bits 8 to 11: Reserved area • Bits 12 to 14: Processor interrupt priority level (IPL) Processor interrupt priority level (IPL) is configured with ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Reset Reset There are two types of reset: a hardware reset and a software reset (See “Software Reset” for details on software resets.) Hardware reset There ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Reset Software reset When the PM0 register's PM03 bit is set “1” (microcomputer reset), the CPU, SFR, and pins of the microcomputer are initialized similar to ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Reset Table 1.5.1. Pin status at RESET for User / Boot operating modes Pin name User Mode (CNV Input port (high impedance ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Reset Voltage detection circuit The voltage detection circuit has monitoring circuits to check the input voltage of the V circuits monitor the the input voltage at ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Reset ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Reset Typical operation of hardware reset 2 (Note) V DET4 V DET3r DET3 V DET3s V SS RESET Internal reset signal VC13 bit ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Reset Voltage detection circuit A V detection interrupt request is generated when the input voltage of the V DET4 V or drops under V DET4 DET4 ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Reset 2. Limitations on wait instructions with peripheral clocks turned off If the WAIT instruction is executed when bit VC13 of the VCR1 register is equal ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Special Function Registers Special Function Registers Figures 1.6.1 through 1.6.5 display special function register (SFR) names, addresses, acronyms, and reset values. Address 0000 16 0001 16 ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Special Function Registers Address 0040 16 0041 16 0042 16 0043 16 0044 INT3 interrupt control register 16 0045 16 0046 16 0047 16 0048 INT5 ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Special Function Registers Address 0340 16 0341 16 0342 Timer A1-1 register (low) 16 0343 Timer A1-1 register (high) 16 0344 Timer A2-1 register (low) 16 ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Special Function Registers Address 0380 Count start flag 16 0381 Clock prescaler reset flag 16 0382 One-shot start flag 16 0383 Trigger select register 16 0384 ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Special Function Registers Address 03C0 A-D register 0 (low) 16 03C1 A-D register 0 (high) 16 03C2 A-D register 1 (low) 16 03C3 A-D register 1 ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Processor Mode Processor Mode This device functions in single-chip mode only. In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Processor Mode Processor mode register 2 (Note Bit symbol Nothing is assigned. ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Processor Mode Software wait A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address 0005 ) ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Generating Circuit Clock Generating Circuit The clock generating circuit contains three oscillator circuits as follows: (1) Main clock generating circuit (2) Sub clock generating circuit ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Generating Circuit Figure 1.8.1 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Generating Circuit Clock Control Figure 1.8.3 shows the block diagram of the clock generating circuit. Sub-clock generating circuit X CIN CM04 CM10=1(stop mode ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Generating Circuit The following paragraphs describes the clocks generated by the clock generating circuit. (1) Main clock The main clock is generated by the main ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Generating Circuit System clock control register 0 (Note Symbol CM0 Bit symbol Reserved bit Reserved bit ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Generating Circuit Peripheral clock select register (Note Bit symbol PCLK0 PCLK1 ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Oscillation Stop Detection Oscillation Stop Detection Function The oscillation stop detection function detects abnormal stopping of the clock by causes such as opening and shorting of ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Oscillation Stop Detection Oscillation stop detection register (Note Symbol 0 0 CM2 Bit symbol CM20 CM21 CM22 ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Oscillation Stop Detection Oscillation stop detection bit (CM20) You can start the oscillation stop detection by setting this bit to “1”. The detection is not executed ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Oscillation Stop Detection Figure 1.8.7. Flow of the judgment SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Oscillation stop detection interrupt or watchdog timer interrupt is generated Read CM22 NO ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Oscillation Stop Detection Stop Mode Writing “1” to the all-clock stop control bit (bit 0 at address 0007 puter enters stop mode. In stop mode, the ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Status Transition of BCLK Status Transition of BCLK Power dissipation can be reduced and low-voltage operation achieved by changing the count source for BCLK. Table 1.8.3 ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Status Transition of BCLK Table 1.8.3. Operating modes dictated by settings of system clock control registers 0, 1, and 2 CM2 register Modes High-speed mode Midium- ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Power Control Power control The following is a description of the three available power control modes: Modes Power control is available in three modes. (a) Normal ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Power Control Transition of stop mode, wait mode CM10=1 All oscillators stopped Stop mode Interrupt Interrupt All oscillators stopped Stop mode CM10=1 CM10=1 All oscillators stopped ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Protection Protection The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Interrupts Interrupts Type of Interrupts Figure 1.9.1 lists the types of interrupts. Software Interrupt Hardware Note: Peripheral I/O interrupts are generated by the peripheral functions built ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Interrupts Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. • Undefined instruction interrupt An undefined instruction interrupt occurs when ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Interrupts Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts. (1) Special interrupts Special interrupts are non-maskable interrupts. • ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Interrupts Interrupts and Interrupt Vector Tables If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. The ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Interrupts • Variable vector tables The addresses in the variable vector table can be modified by user’s settings. The first address of the variable vector table ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Interrupts Interrupt Control This section describes how to enable or disable maskable interrupts and how to set the priority to be accepted. The discussion here does ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Interrupts Interrupt control register (Note Bit symbol Nothing is assigned attempt to write to these ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Interrupts Interrupt Enable Flag (I flag) The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to “1” enables ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Interrupts Rewrite the interrupt control register To rewrite the interrupt control register point that does not generate the interrupt request for that ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Interrupts Interrupt Sequence This section describes an interrupt sequence — what are performed over a period from the time an inter- rupt is accepted until the ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Interrupts Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the DIVX instruction (without wait). Time ( ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Interrupts Saving Registers In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC) are saved in the ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Interrupts The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer (Note the ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Interrupts Returning from an Interrupt Routine Executing a REIT instruction at the end of an interrupt routine returns the contents of the flag register (FLG) as ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Interrupts Priority level of each interrupt INT1 Timer B2 Timer B0 Timer A3 Timer A1 INT3 INT0 Timer B1 Timer A4 Timer A2 UART1 receive UART0 ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Interrupts INT Interrupt INT0, INT1, INT3 to INT5 are triggered by the edges of external inputs. The edge polarity of the interrupt is selected using the ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Interrupts NMI Interrupt If enabled, an NMI interrupt is generated when the input to the P8 NMI interrupt is a non-maskable external interrupt. The pin level ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Interrupts Address Match Interrupt An address match interrupt is generated when the address match interrupt address register contents match the program counter value. Four address match ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Precautions for Interrupts Precautions for Interrupts (1) Reading address 00000 • Do not read address 00000 When a maskable interrupt is generated, the CPU reads the ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Precautions for Interrupts • When the polarity of the INT sometimes set to “1”. After changing the polarity, set the interrupt request bit to “0”. Figure ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Watchdog Timer Watchdog Timer The watchdog timer has the function of detecting when the program is out of control. Therefore, we recom- mend using the watchdog ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Watchdog Timer BCLK HOLD Write to the watchdog timer start register (address 000E ) 16 RESET Figure 1.10.1. Block diagram of watchdog timer Watchdog timer control ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. DMAC DMAC This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU. DMAC shares ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. DMAC Table 1.11.1. DMAC specifications Item No. of channels Transfer memory space cessed) Maximum No. of bytes transferred 128K bytes (with 16-bit transfers) or 64K bytes ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. DMAC DMA0 request cause select register Nothing is assigned attempt to write to these bits, write ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. DMAC DMA1 request cause select register Bit symbol DSEL0 DSEL1 DSEL2 DSEL3 Nothing is assigned attempt ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. DMAC DMAi source pointer ( (b19) (b16)(b15) (b23 DMAi destination pointer ( (b19) (b16) (b15) (b23) ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. DMAC (1) Transfer cycle The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area (source read) ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. DMAC (1) 8-bit transfers 16-bit transfers and the source address is even. BCLK Address CPU use bus RD signal WR signal Data CPU use bus (2) ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. DMAC Table 1.11.2. No. of DMAC transfer cycles Transfer Unit Bus Width 8-bit transfers 16 bit (DMBIT="1") 16-bit transfers 16 bit (DMBIT="0") Coefficient j, k Internal ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. DMAC DMA enable bit Setting the DMA enable bit to “1” makes the DMAC active. The DMAC carries out the following opera- tions at the time ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. DMAC (3) The priorities of channels and DMA transfer timing If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Timers Timers There are eight 16-bit timers. These timers can be classified by function into timers A (five) and timers B (three). All these timers function ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Timers f 2 PCLK0 bit = "0" 1 • PCLK0 bit = "1" • Ring oscillator 1/8 clock ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Timer A Timer A Figure 1.12.3 shows the block diagram of timer A. Figures 1.12.4 to 1.12.6 show the timer A-related registers. Except in event counter ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Timer A Timer Ai register (Note 1) (b15) (b8 Count start flag Up/down flag (Note ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Timer A One-shot start flag Note: Set the corresponding port direction register Trigger select ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Timer A (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 1.12.1.) Figure 1.12.7 shows the timer Ai mode ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Timer A Event Counter Mode In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can count a ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Timer A Table 1.12.3. Timer specifications in event counter mode (when processing two-phase pulse signal with timers A2, A3, and A4) Item Count source • Two-phase ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Timer A Timer Ai mode register (When using two-phase pulse signal processing TMOD0 ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Timer A (3) One-shot timer mode In this mode, the timer operates only once. (See Table 1.12.4.) When a trigger occurs, the timer starts up and ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Timer A (4) Pulse width modulation (PWM) mode In this mode, the timer outputs pulses of a given width in succession. (See Table 1.12.5.) In this ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Timer A Condition : Reload register = 0003 (rising edge of TA Count source H TA pin iIN input signal L H PWM pulse output from ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Timer B Timer B Figure 1.13.16 shows the block diagram of timer B. Figures 1.13.17 and 1.13.18 show the timer B-related registers. Use the timer Bi ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Timer B Timer Bi register (Note) (b15) (b8 Ä Timer mode Counts the timer's period Ä Event counter mode Counts external pulses input ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Timer B (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 1.13.6.) Figure 1.13.19 shows the timer Bi mode ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Timer B (2) Event counter mode In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.13.7.) Figure 1.13.20 shows ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Timer B (3) Pulse period/pulse width measurement mode In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Timer B When measuring measurement pulse time interval from falling edge to falling edge Count source H Measurement pulse L Reload register counter transfer timing Timing ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Three-Phase Motor Control Timer Function Three-Phase Motor Control Timer Function Use of more than one built-in timer A and timer B provides the means of outputting ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Three-Phase Motor Control Timer Function Three-phase PWM control register Symbol INVC1 Bit symbol INV10 INV11 INV12 INV13 ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Three-Phase Motor Control Timer Function Three-phase output buffer register Bit Symbol DU0 DUB0 DV0 DVB0 DW0 DWB0 ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Three-Phase Motor Control Timer Function Timer Ai (i= register (Notes 1, 4) (b15) (b8 · Timer mode Counts an internal count ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Three-Phase Motor Control Timer Function Trigger select register Note: Set the corresponding port direction register ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Three-Phase Motor Control Timer Function Three-phase motor driving waveform output mode (three-phase PWM output mode) Setting “1” in the mode select bit (bit 2 at 0348 ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Three-Phase Motor Control Timer Function Figure 1.14.7 shows the block diagram for three-phase PWM output mode. When selecting output polar- ity “L” active in three-phase PWM ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Three-Phase Motor Control Timer Function Figure 1.14.7. Block diagram for three-phase PWM output mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Renesas Technology Corp. M16C/26 Group 101 ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Three-Phase Motor Control Timer Function Triangular wave modulation To generate a PWM waveform of triangular wave modulation, set “0” in the modulation mode select bit (bit ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Three-Phase Motor Control Timer Function waveform, which has the opposite phase of the U phase waveform, are the same as in generating a U phase waveform. ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Three-Phase Motor Control Timer Function Assigning certain values to DU0 (bit 0 at 034A 034B ) and DUB1 (bit 1 at 034B 16 that is, to ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Three-Phase Motor Control Timer Function Figures 1.14.1 to 1.14.5 show registers related to timers for three-phase motor control. Sawtooth modulation To generate a PWM waveform of ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Three-Phase Motor Control Timer Function A carrier wave of sawtooth waveform Carrier wave Signal wave Timer B2 Trigger signal for timer Ai start (timer B2 overflow ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Three-Phase Motor Control Timer Function A carrier wave of sawtooth waveform Carrier wave Signal wave Timer B2 Interrupt occurs. Rewriting the value of timer A4. Trigger ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Serial I/O Serial I/O Serial I/O is configured as three channels: UART0, UART1, and UART2. UARTi ( UART0, UART1 and UART2 each ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Serial I/O (UART0) RxD 0 Clock source selection CLK1 to CLK0 1SIO or 2SIO Internal 01 2 CKDIR=0 f 8SIO 10 2 ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Serial I/O PAR 1SP disabled SP SP PAR RxDi 2SP PAR enabled PAR enabled 2SP SP SP PAR 1SP PAR disabled 0 Figure ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Serial I/O No reverse RxD data RxDi reverse circuit Reverse PAR disabled 1SP SP SP PAR 2SP PAR enabled PAR enabled 2SP SP ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Serial I/O UARTi transmit buffer register (Note) (b15) (b8 UARTi receive buffer register (b15) (b8 UARTi bit rate generator (Note ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Serial I/O UARTi transmit/receive mode register Symbol UiMR(i=0,1) 0 Bit symbol SMD0 Serial I/O mode select bits SMD1 ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Serial I/O UART2 transmit/receive mode register Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY PRYE IOPOL UART2 transmit/receive ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Serial I/O UARTi transmit/receive control register 1 (i=0, 1) Symbol UiC1(i=0,1) Bit symbol Nothing ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Serial I/O UART transmit/receive control register Symbol UCON Bit symbol U0IRS U1IRS U0RRM U1RRM CLKMD0 CLKMD1 RCSP ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Serial I/O UART2 special mode register Bit symbol IICM2 CSC SWC ALS STAC SWC2 SDHI Nothing is ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Serial I/O UART2 special mode register Bit symbol STAREQ RSTAREQ STPREQ STSPSEL ACKD ACKC SCLHI SWC9 Note: ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Synchronous Serial I/O Mode Clock Synchronous Serial I/O Mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Synchronous Serial I/O Mode Table 1.15.3. Specifications of clock synchronous serial I/O mode (2) Item Select function • CLK polarity selection • LSB first/MSB first ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Synchronous Serial I/O Mode Table 1.15.4. Registers used in clock synchronous serial I/O mode and the register values set Register Bit UiTB(Note3 ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Synchronous Serial I/O Mode UARTi transmit/receive mode register (i Bit symbol ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Synchronous Serial I/O Mode Table 1.15.5 lists the functions of the input/output pins during clock synchronous serial I/O mode. This table shows the pin functions ...

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Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Synchronous Serial I/O Mode • Example of transmit timing (when internal clock is selected) Transfer clock 1 Transmit enable 0 Data is set in UARTi ...

Page 133

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Synchronous Serial I/O Mode (a) Polarity select function As shown in Figure 1.15.13, the CLK polarity select bit (bit 6 at addresses 03A4 allows selection ...

Page 134

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Synchronous Serial I/O Mode (c) Transfer clock output from multiple pins function (UART1) This function allows the setting two transfer clock output pins and choosing ...

Page 135

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Synchronous Serial I/O Mode (f) CTS/RTS separate function (UART0) This function separates CTS from the P6 pin. To use this function, set the register bits ...

Page 136

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Asynchronous Serial I/O (UART) Mode Clock Asynchronous Serial I/O (UART) Mode The UART mode allows transmitting and receiving data after setting the desired transfer rate ...

Page 137

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Asynchronous Serial I/O (UART) Mode Table 1.15.8. Specifications of UART Mode (2) Item Select function • Serial data logic switch (UART2) This function is reversing ...

Page 138

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Asynchronous Serial I/O (UART) Mode Table 1.15.9 Registers used in UART mode and the register values set Register Bit UiTB UiRB 0 ...

Page 139

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Asynchronous Serial I/O (UART) Mode UARTi transmit / receive mode registers Bit symbol Reserved Note: Set the ...

Page 140

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Asynchronous Serial I/O (UART) Mode Table 1.15.10 lists the functions of the input/output pins during UART mode. Note that for a period from when the ...

Page 141

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Asynchronous Serial I/O (UART) Mode • Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) Transfer clock 1 ...

Page 142

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Asynchronous Serial I/O (UART) Mode • Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) Transfer clock 1 ...

Page 143

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Asynchronous Serial I/O (UART) Mode (a) Function for switching serial data logic (UART2) When the data logic select bit (bit 6 of address 037D the ...

Page 144

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Asynchronous Serial I/O (UART) Mode (b) TxD, RxD I/O polarity reverse function (UART2) This function reverses/inverts T output (including the start bit, stop bit(s), and ...

Page 145

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Asynchronous Serial I/O (UART) Mode Clock-Asynchronous Serial I/O Mode (used for SIM interface) The SIM (Subscriber Identity Module) interface is used for connecting the microcomputer ...

Page 146

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Asynchronous Serial I/O (UART) Mode Transfer clock 1 Transmit enable bit(TE) 0 Data is set in UART2 transmit buffer register 1 Transmit buffer empty flag(TI) ...

Page 147

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Asynchronous Serial I/O (UART) Mode (a) Function to output a parity error signal During reception, with the error signal output enable bit (bit 7 of ...

Page 148

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Asynchronous Serial I/O (UART) Mode Figure 1.15.27 shows the example of connecting the SIM interface. Connect T apply pull-up. Microcomputer Figure 1.15.27. Connecting the SIM ...

Page 149

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. UART2 Special Mode Register UART2 Special Mode Register The UART2 special mode register (address 0377 Bit 0 of the UART2 special mode register are used as ...

Page 150

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. UART2 Special Mode Register TxD2/SDA2 Timer I/O Selector UARTi Noize Filter Timer Start condition detection Stop condition detection Falling edge detection RxD2/SCL2 I/O ...

Page 151

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. UART2 Special Mode Register Setting “1” in the I2C mode select bit (IICM) causes ports to work as data transmission-reception terminal SDAi, clock input-output terminal SCLi, ...

Page 152

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. UART2 Special Mode Register Some other functions added are explained here. Figure 1.15.29 shows their workings. Bit 4 of the UART2 special mode register is used ...

Page 153

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. UART2 Special Mode Register 2 UART2 Special Mode Register 2 UARTi special mode register 2 (address 0376 Bit 0 of the UART2 special mode register 2 ...

Page 154

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. UART2 Special Mode Register 2 Bit 3 of the UARTi special mode register 2 are used as the SDAi output stop bit. Setting this bit to ...

Page 155

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. UART2 Special Mode Register 3 UART2 Special Mode Register 3 Bit 1 of UART2 special mode register 3 (address 0375 shows UART2 special mode register 3. ...

Page 156

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. UART2 Special Mode Register 4 UART2 Special Mode Register 4 Bit 0 of UART2 special mode register 4 (address 0374 the SCL, SDA output select bit ...

Page 157

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. UART2 Special Mode Register 4 Table 1.15.17. Functions changed by SCL, SDA output select bit Function SCL, SDA output Start/stop condition interrupt factor (1) When slave ...

Page 158

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Serial Interface Special Function Serial Interface Special Function UARTi can control communications on the serial bus (Figure 1.15.32). The master outputting the transfer clock transfers data ...

Page 159

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Serial Interface Special Function • Clock Phase Setting With bit 1 of UART2 special mode register 3 (addresses 036D UART2 transmission-reception control register 0 (addresses 03A4 ...

Page 160

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Serial Interface Special Function "H" Slave control input "L" "H" Clock input "L" (CKPOL=0, CKPH=0) Clock input "H" (CKPOL=1, CKPH=0) "L" "H" Data output timing "L" ...

Page 161

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. A-D Converter A-D Converter The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. Pins P10 to P10 also ...

Page 162

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. A-D Converter CKS2=0 f 1/3 AD CKS2=1 V REF Resistor ladder VCUT VCUT=1 Successive conversion register Addresses A-D register 0(16) (03C1 , 03C0 ) ...

Page 163

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. A-D Converter A-D control register 0 (Note 1) Symbol ADCON0 Bit symbol CH0 CH1 CH2 MD0 MD1 TRG ...

Page 164

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. A-D Converter A-D control register 2 (Note Symbol ADCON2 Bit symbol SMP Reserved bits ...

Page 165

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. A-D Converter (1) One-shot mode In one-shot mode, the pin selected using the analog input pin select bits , is used for one-shot A-D conversion. Table ...

Page 166

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. A-D Converter (2) Repeat mode In repeat mode, the pin selected using the analog input pin select bits , is used for one-shot A-D conver- sion. ...

Page 167

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. A-D Converter (3) Single sweep mode In single sweep mode, the pins selected using the A-D sweep pin select bits, are used for one-by-one A- D ...

Page 168

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. A-D Converter (4) Repeat sweep mode 0 In repeat sweep mode 0, the pins selected using the A-D sweep pin select bits , are used for ...

Page 169

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. A-D Converter (5) Repeat sweep mode 1 In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins ...

Page 170

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. A-D Converter (a) Sample and Hold Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D4 sample and hold ...

Page 171

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Programmable I/O Ports Programmable I/O Ports There are 38 programmable I/O ports: P1 can be set independently for input or output using the direction register. A ...

Page 172

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Programmable I/O Ports ...

Page 173

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Programmable I/O Ports Data bus Data bus Input to respective peripheral functions ...

Page 174

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Programmable I/O Ports NMI Enable P8 5 Data bus NMI Interrupt Input Port Xc Select bit P8 7 Data bus Port Xc Select bit Direction register ...

Page 175

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Programmable I/O Ports Port Pi direction register Bit symbol PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7 Port ...

Page 176

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Programmable I/O Ports Port Pi register Symbol 10) Bit symbol Pi_0 Pi_1 Pi_2 ...

Page 177

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Programmable I/O Ports Pull-up control register Symbol Bit symbol Nothing is assigned attempt to write ...

Page 178

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Programmable I/O Ports Port control register Bit symbol PCR0 Nothing is assigned attempt to write to ...

Page 179

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Electrical Characteristics Electrical Characteristics Table 1.18.1. Absolute maximum ratings S Parameter ymbol V Supply voltage CC AV Analog supply voltage CC Input ...

Page 180

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Electrical Characteristics Table 1.18.3. Recommended operating conditions (referenced Topr = – Symbol V CC Supply voltage ...

Page 181

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Electrical Characteristics Table 1.18.4. A-D conversion characteristics (Notes 1–3) Symbol Parameter – Resolution INL ...

Page 182

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Electrical Characteristics Table 1.18.6. Low Voltage Detection Circuit Electrical Characteristics (Note Parameter ...

Page 183

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Electrical Characteristics (Vcc = 5V) Table 1.18.10. Electrical characteristics (referenced Topr = – Symbol Parameter HIGH output P1 ...

Page 184

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Electrical Characteristics (Vcc = 5V) Timing requirements (referenced 5V 0V, at Topr = – ...

Page 185

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Electrical Characteristics (Vcc = 5V) Timing requirements (referenced 5V 0V, at Topr = – ...

Page 186

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Electrical Characteristics (Vcc = 5V) Timing requirements (referenced 5V 0V, at Topr = – ...

Page 187

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Electrical Characteristics (Vcc = 3V) Table 1.18.24. Electrical characteristics (referenced Topr = – 20 unless otherwise specified) Symbol Parameter HIGH output P1 to ...

Page 188

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Electrical Characteristics (Vcc = 3V) Timing requirements (referenced 3V 0V, at Topr = – ...

Page 189

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Electrical Characteristics (Vcc = 3V) Timing requirements (referenced 3V 0V, at Topr = – ...

Page 190

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Electrical Characteristics (Vcc = 3V) Timing requirements (referenced 3V 0V, at Topr = – ...

Page 191

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Timing TAi input IN TAi input OUT TAi input OUT (Up/down input) During event counter mode TAi input IN (When count on falling edge is selected) ...

Page 192

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Flash Memory Outline Performance Table 1.19.1 shows the outline performance of the M16C/26 (flash memory version). Table 1.19.1. Outline performance of the M16C/26 (flash memory version) ...

Page 193

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Flash Memory Flash Memory The M16C/26 (flash memory version) contains the flash memory that can be rewritten with a single voltage. For this flash memory, three ...

Page 194

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. CPU Rewrite Mode (Flash Memory Version) CPU Rewrite Mode The CPU rewrite mode is used to perform a read, program, or erase operation on the internal ...

Page 195

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. CPU Rewrite Mode (Flash Memory Version) commands. In CPU rewrite mode (whether EW0 or EW1), make sure all software commands and data are written to and ...

Page 196

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. CPU Rewrite Mode (Flash Memory Version) Erase-Suspend Feature The M16C/26 Flash ROM has been designed to be more compact and require a smaller layout footprint. This, ...

Page 197

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. CPU Rewrite Mode (Flash Memory Version) EW1: In EW1, program code is executed out of the FLASH. First FMR40 (SUSPEND_ENABLE) must be set to allow the ...

Page 198

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. CPU Rewrite Mode (Flash Memory Version) Register Description Figure 1.20.1 shows the flash identification register, flash memory control register 0 and flash memory control register 1. ...

Page 199

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. CPU Rewrite Mode (Flash Memory Version) Flash memory control register 1 (FMR1): Bit 1 allows the user to enter EW1 mode. This bit is relevant only ...

Page 200

Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. CPU Rewrite Mode (Flash Memory Version) Flash memory control register Flash memory control register 1 ...