C8051F500-IM Silicon Laboratories Inc, C8051F500-IM Datasheet - Page 238
C8051F500-IM
Manufacturer Part Number
C8051F500-IM
Description
IC 8051 MCU 64K FLASH 48-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F50xr
Specifications of C8051F500-IM
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
48-QFN
Mfg Application Notes
LIN Bootloader AppNote
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
40
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 32x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
40
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F500DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 32 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1530 - ADAPTER PROG TOOLSTICK F500336-1529 - PLATFORM PROG TOOLSTCK F500336-1527 - KIT DEV FOR C8051F50X336-1526 - BOARD PROTOTYPE W/C8051F500
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1511-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F500-IM
Manufacturer:
Silicon Labs
Quantity:
135
Part Number:
C8051F500-IMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
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C8051F50x/F51x
23.5.2. Read Sequence (Master)
During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will
be a transmitter during the address byte, and a receiver during all data bytes. The SMBus interface gener-
ates the START condition and transmits the first byte containing the address of the target slave and the
data direction bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then
received from the slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more
bytes of serial data. An interrupt is generated after each received byte.
Software must write the ACK bit at that time to ACK or NACK the received byte. Writing a 1 to the ACK bit
generates an ACK; writing a 0 generates a NACK. Software should write a 0 to the ACK bit for the last data
transfer, to transmit a NACK. The interface exits Master Receiver Mode after the STO bit is set and a
STOP is generated. The interface will switch to Master Transmitter Mode if SMB0DAT is written while an
active Master Receiver. Figure 23.6 shows a typical master read sequence. Two received data bytes are
shown, though any number of bytes may be received. Notice that the ‘data byte transferred’ interrupts
occur before the ACK cycle in this mode.
238
S
Received by SMBus
Interface
Transmitted by
SMBus Interface
SLA
Figure 23.6. Typical Master Read Sequence
R
A
Data Byte
Interrupts
Rev. 1.2
A
S = START
P = STOP
A = ACK
N = NACK
R = READ
SLA = Slave Address
Data Byte
N
P
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